Page 100 - Handout Digital Electronics

When S = 0 and R = 0, Q = 1 and Q = 1. This input combination is not allowed as it is also a race
condition or ambiguous case. The rest of the input combinations do not bring about ambiguous cases.
See state table below:

S R Q Q Name
0 0 x x Not allowed
0 1 0 1 Reset (clear to 0)
1 0 1 0 Set to 1 (store)
1 1 1 0 Set to 1 (store)

SR latch symbol

As can be seen from the state table above, the SR latch implemented on NAND gates only is also
affected by the ambiguous case. The attempt to eliminate this ambiguous case continued with the
introduction of the NAD gates and the clock to the SR latch.

12.3 Clocked SR flip flop
In the clocked SR flip flop, AND gates and the clock were introduced. The AND gates are usually used
for control purposes because of the operation characteristic of an AND where the output is a binary one
(1) only and only when both inputs are binary one. The clock was introduced to make sure that the latch
does not change states arbitrary but should change at regular intervals of the clock pulse. (See clocked
SR flip flop logic circuit below).

Figure 35: Clocked SR flip flop implemented on AND and NOR gates
The experimental truth table is shown below:

C S R Q Q

0 0 0 0 1
0 0 1 0 1

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