Page 102 - Handout Digital Electronics

12.4 Flip flop Control Signals

Control signals associated with flip flops are:

• Clock

• Pr eset

• Clear
The Clock is used to allow data from external input sources into the flip flop, and it is also used for
synchronization purposes.

The Pr eset control signal is used to force the flip flop into state one (store) regardless of the clock or

the value at the input lines. The Pr eset control signal was one of the options used to avoid the
ambiguous case in the clocked SR flip flop.

The Clear control signal is used to clear the flip flop regardless of the clock or values in the input lines.

The Pr eset and Clear are low level signals which means they operate on the falling edge of a clock
pulse, that is they are activated by a low-level signal (binary 0). So as such they are not allowed to be
binary zeros at the same time.

Below is an example of a truth table of a clocked SR flip flop were the Pr eset and Clear control
signals have been added.

C S R Q
Pr eset Clear Q
0 1 1 0 0 1 0
1 0 1 1 0 0 1
1 1 1 1 0 1 0
1 0 1 1 0 0 1
0 1 1 1 0 1 0

It is clear from the above state table (truth) that whenever Pr eset is equal to 0, the flip flop is forced
into state 1 (store), for example the first input combination: Pr eset = 0, Clear = 1, C = 1, S = 0 and R
=0, Q =1 and Q = 0. In the absence of the Pr eset and Clear control signals this input combination
would have been Q = 0 and Q = 1. From the above state table, it is also clear that whenever Clear = 0
the flip flop is driven into state 0 (Reset or Clear to zero). In the truth table above, there are two cases
when Clear = 0 and the outputs in both cases are Q = 0 and Q = 1. The above state table shows that

There are no cases where Pr eset = Clear equals to zero (0).When Pr eset = Clear = 1, the two control
signals are ignored and the conventional truth table is followed (see truth table)

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