Page 99 - Handout Digital Electronics

The SR flip flop has two input lines S and R. S stands for Set and the R stands for Reset. The S drives
the latch into state 1 (store) when it is equal to 1 and the R clears the latch to state 0, when it is equal to
1. The two output lines Q and (not Q) Q‟ are always complementary. The above latch is an example of
an asynchronous sequential circuit. The output Q‟ (not Q) is fed back to the upper NOR gate and the Q
output is fed back to the lower NOR gate. The not Q is also written as Q . For purposes of
standardization when propagating the signals, signals are propagated from the S input first and then the
R. If one starts propagating the signals from the R input the state tables will not be the same.

The above asynchronous latch operates as follows:

When S = 0 and R = 0, output Q = 0 and Q = 1

When S = 0 and R = 1, output Q = 0 and Q = 1

When S = 1 and R = 0, output Q = 1 and Q = 0.

The input combination S = 1 and R = 1 is not allowed and is known by several names such as „race
condition‟,‟ indeterminate‟ state and „ambiguous‟ state. This input combination gives the output Q = Q

= 0. The outputs Q and Q must never be the same. The race condition means that whichever input line
changes first determines the output. This means that one cannot predict the next state with certainty. The
operation of the SR latch is summarized by the state table below:

S R Q Q Name
0 0 0 1 No change
0 1 0 1 Reset (clear to 0)
1 0 1 0 Set to 1 (store)
1 1 x X Not allowed

The SR latch is not commercially available because of the race condition or the ambiguous state. There
were several attempts made to eliminate the race condition in the SR latch to no avail.

The SR latch can also be implemented on NAND gates only. See the SR latch logic circuit implemented
on NAND gates only below:

Figure 34: SR latch implemented on NAND gates only
The SR latch implemented on NAND gates only operates as follows:

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