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Digital Logic Circuits 30
DESIGN
Design Procedure:
Specification State Diagram Sta
Excitation Table Karnaugh Map
Example: 2-bit Counter -> 2 FF's cur
x=0
sta
x=1 00 x=1 A
0
x=0 01 11 x=0
0
x=1 x=1 0
0
10
1
x=0 1
1
1
B BB B
dd d d
d 1 x d dx 1 d x d 1 x
d d A 1 A1 d d 1
A d A
d d
Ja Ka Jb Kb
Ja = Bx Ka = Bx Jb = x Kb = x
Computer Organization
