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wafer, and there’s an additional step required to smooth off the surface of the puck before you can do another laser split.”
Process time and throughput vary greatly among the pro- cess steps in the wafering sequence. Edge grind is one of the shortest steps, at somewhere between five and 10 minutes per wafer. Rhoades noted that there are many assumptions around the lapping and surface-grinding approach, and they depend on how many wafers you are willing to run per batch. “Let’s assume you have a standard or typical batch size of 12 to 16 wafers per batch, and it takes a couple of hours for the lapping and post-lap cleaning process to complete,” he said. “Surface grinding is faster, about five to 10 minutes per wafer, and if something goes wrong, you will lose only one or two wafers instead of losing the entire batch. In the last cou- ple of years, grind-wheel manufacturers have really focused on silicon carbide to reduce the grind time, and so the pro- cess times per wafer are still coming down.”
Polishing is similar to lapping; it takes up to a couple of hours per batch. Typical production cleaning lines have throughputs that are in the range of 20 to 50 wafers per hour, depending on the size of the batch tanks, so this step is not generally a capacity bottleneck.
The need for an epitaxial layer, and the associated thickness and dopant profile, is part of the device designer’s decision. It relates primarily to the voltage at which the device needs to operate. “The reason we consider epitaxy as optional is that some devices require an epitaxial layer and some devices don’t,” said Rhoades. “So it depends on the type of device that the customer intends to build, whether they need epi- taxy or not. If epitaxy is needed, the process generally takes anywhere from 30 minutes to several hours per wafer. The thicker the layer, the longer it takes to grow.”
Standard wafers
Rhoades noted that the majority of current wafer pro- duction is either 100-mm or 150-mm diameter (typical 300- or 350-μm thickness). Both are in strong demand, but 150 mm is currently where most of the growth is taking place in the industry. Some companies have started to adopt new processing methods for 150 mm, such as laser split- ting instead of wire sawing. “There is a big competition in the industry right now to see which method is better for 150-mm wafers, and at the same time, the industry is trying very hard to get to a 200-mm wafer diameter,” said Rhoades.
The 200-mm wafer size is desirable not only because you can produce more devices on each wafer but also because it potentially enables customers to retool some fabs currently running older generations of silicon technology. The oppor-
tunity to leverage that installed device fabrication capacity would pave the way for many more SiC devices to be built, ensuring strong adoption and driving the EV market.
“There’s a lot of push from a lot of companies to try to get to 200-mm silicon carbide, and so far, two companies have announced they are able to produce 200-mm wafers,” said Rhoades. “These are Cree and II-VI, but they are not yet sell- ing on the open market. They are using all their production capacity for internal development and internal use. Also, ST has recently announced that it can now grow 200-mm silicon carbide.”
One of the interesting process implications of getting to 200-mm–diameter wafers is that batch lapping and batch polishing are much lower-throughput due to simple geom- etry. Whereas 100-mm or 150-mm wafers may yield 12 or 16 wafers or more per batch, you get only three or four 200-mm wafers per batch. “So the economics start to strongly favor a single-wafer approach, namely a single-wafer grinder and single-wafer polisher,” said Rhoades. “Not only do you get better control over each wafer, but you also actually get higher throughput out of the system because you can run the processes more aggressively on a single-wafer tool than you can on a batch tool.”
SiC is usually much thinner than a standard silicon wafer, by roughly 50%, and it is highly prone to cracking and chipping. This requires most process equipment to be redesigned to reduce the risk of breakage for SiC.
SiC is a green product in terms of electrical efficiency in the systems in which it is used. However, the production process for growing SiC boules requires a lot of energy, and many companies are working on using only clean energy when- ever possible. In addition, very high growth temperatures, above 2,000˚C, imply considerable expenditures for energy- management and safety-control systems. Fortunately, the system-level efficiency gains of SiC devices over the lifetime of the end-use products are more than sufficient to pay back the energy investment required to grow and process the initial SiC material.
This article was originally published on Power Electronics News on Aug. 19, 2021.
Maurizio Di Paolo Emilio
is editor-in-chief of Power Electronics News and EEWeb.
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AspenCore News Coverage Improving the SiC Wafer Process