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“Regarding the gate oxide reliability issue, GeneSiC’s SiC MOSFETs are designed with maximum gate oxide fields significantly below 4 MV/cm,” said Singh. “The second aspect with respect to oxide reliability is the quality of the gate oxide–SiC interface. The gate oxidation process used for GeneSiC’s SiC MOSFET fabrication ensures a very low defect density, both within the gate oxide and at the gate oxide–SiC interface.”
Another important aspect related to SiC MOSFET transis- tors is the stability of the built-in body diode. In traditional H-bridge power-conversion circuits, the MOSFET body diode conducts the rated current during the free-wheeling opera- tion. SiC MOSFETs from several leading device vendors have
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incurred significant degradation of the device characteris- tics resulting from the operation of the body diode.
“This [body-diode stability] aspect is more related to the SiC material — to certain defects in the starting SiC sub- strate wafers and how you grow the silicon carbide epi- taxial layer,” said Singh. “How your layers are designed and what kind of growth techniques you use determine the body-diode stability.”
Sometimes, it is easy to confuse the reliability of a compo- nent with its robustness. The latter is a parameter that certi- fies the extent of electrical abuse that the device can with- stand, even for short periods of time. There are operations that can be carried out very well, for instance, with Schottky diodes. Others cannot be carried out, as the devices cannot withstand operation under avalanche-breakdown conditions.
GeneSiC guarantees its devices “to the highest robustness levels in the industry,” said Singh. “Our SiC MPS rectifiers and MOSFETs are 100% avalanche-tested. Our SiC MOSFETs have the longest short-circuit time for the lowest RDS(on), so a good tradeoff shall be found here.”
This article was originally published on Power Electronics News on Feb. 25, 2021.
Stefano Lovati
is a technical writer for Power Electronics News and EEWeb.
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