Page 53 - LFT Presentation-Jan2021_compressed (1)

ML/AI - FPGA Acceleration

Customer Requirement - Develop 10G/40G Network stack with specific UDP packet interception capability

LFT’s Solution

• Solution built using Intel’s Acceleration Stack for Intel’s

Xeon CPU with FPGA; CCIP interface on the FPGA
side & OPAE interface on host SW side

• Developed CPU-side Linux App that program Filter
Rules ( Port #, MAC address, etc) and can

send/receive packets

• Developed CPU-side Linux custom NIC Driver

• FPGA-side VirtIO DMA functionality to transfer packets
to/from CPU to FPGA with 10/40 Gbs speed support

• Reused LFT’s UDP Packet Interceptor IP

• Reused LFT’s Payload Extractor IP that included

• Terminating UDP protocol.
• Assembling and Buffering Payload

• DMAs to Megh Linux App

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