Page 8 - LFT Presentation Jan2021 55SA
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Deep High-Speed Serial Protocols Expertise









               • PCIe Gen1/2/3/4/5
                                                                                                  • Optical/Electrical- Embedded Clock


               • Ethernet 1G/10G/40G/100G
                                                                                                  • Combine multiple lane for short distance


               • STM-1/4/16/64
                                                                                                  • Use line coding – 8b/10b,64b/66b

               • OTN1/2/2e/2f

                                                                                                  • Scrambling

               • HDMI1.4 /DisplayPort

                                                                                                  • FPGA SERDEs capable of >32 Gbps

               • Fiber Channel/ARINC 818

                                                                                                  • Common/Independent clock Architecture

               • CPRI ver 4/5/6.0

                                                                                                  • Pretty similar at Layer1& Layer2
               • JESD204B


                                                                                                  • Very high speed using RS FEC
               • DigRFv4 Gen1/Gen2/Gen3



                                                      *This presentation is the intellectual property of Logic Fruit Technologies . Any plagiarism or misuse is punishable according to Indian Laws.
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