Page 4 - coba Revisi Modul Organisasi dan Arsitektur Komputer_Neat
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2.3         Decoder (Decoder) ..................................... 43




                  2.4         Enkoder (Encoder) ..................................... 46




                  2.5         Register Data .............................................. 48




                  2.6         Register Geser ............................................ 50




                  2.7         Pencacah (Counter) .................................... 52




                  2.8         Demultiplexer (Demux) .............................. 54




                  2.9         Penjumlah Setengah (Half Adder) .............. 57




                  2.10  Penjumlah Penuh (Full Adder) ................... 59




                  2.11  Pengurang Setengah (Half Substractor) ..... 63




                  2.12  Pengurang Penuh (Full Substractor) .......... 65




                  2.13  Pembanding (Comparator) ......................... 71




                  2.14  Pengali (Multiplyer) ................................... 73




                  Unit Aritmatika dan Logika ................................ 78




                  3.1         Rangkaian Aritmatika ................................. 79







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