Page 256 - Programmable Logic Controllers, Fifth Edition - Mobile version

Inputs Ladder logic program Output
L1 L2
S1
CTU
COUNT-UP COUNTER CU
S1 PL1
Counter C5:0 DN
Preset 350
Accumulated 0 125
S2
CTU
COUNT-UP COUNTER CU
S2 Counter C5:1 DN
Preset 350
Accumulated 0 100

ADD
ADD
Source A C5:0.ACC 250
Reset
Source B C5:1.ACC
Destination N7:1

PL1
GEQ
GREATER THAN OR EQUAL
Source A N7:1
Source B 350
Reset C5:0
RES

C5:1
RES

Figure 11-5 Counter program that uses the ADD instruction.

arithmetic status bits in the status file are updated. The Overflow (O)—Address S2:0/1, is set to 1 when
description of each bit can be summarized as follows: the result is too large to fit in the destination
register.
Carry (C)—Address S2:0/0, is set to 1 when there is
a carry in the ADD instruction or a borrow in the SUB Zero Bit (Z)—Address S2:0/2, is set to 1 when the
instruction. result of the subtract instruction is zero.

Status Table
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S2:0/ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
S2:1/ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
S2:2/ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
S2:3/ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
S2:4/ 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1
S2:5/ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address S2:0 Table: S2:Status

Figure 11-6 Processor status file S2.

Math Instructions Chapter 11 237

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