Page 875 - Mechatronics with Experiments

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MATLAB , SIMULINK , STATEFLOW, AND AUTO-CODE GENERATION 861
2
6
Define the states Simulate
for modeling each the chart
mode of operation
1 3 5 7
Define the Define Decide how to Debug
interface state actions
to simulink and variables trigger the chart the chart
4
Define the
transitions
between states

FIGURE A.35: Typical steps involved in designing a Stateflow chart as part of a Simulink ®
model.

The typical steps involved in developing a SF chart is shown in Figure A.35.
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Step 1: Input and outputs between Stateflow (SF) and Simulink . The first step
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in designing a typical SF chart is to plan it as part of a Simulink model, and then decide on
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the input–output data and events between the SF block and the Simulink model. The SF
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chart interacts with Simulink through its input and output signals. The input and output
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signals can be data or events needed by SF and Simulink .
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In Simulink , select Stateflow from the Simulink ® Library Browser, then double-
click on it. This will bring up the Stateflow blocks: Chart, Truth Table. Select “Chart” and
drag-and-drop it in the Simulink ® model. Now double-click on the “Chart” block in the
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Simulink model to edit its content using Stateflow Editor.
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In order to define I/O between SF and Simulink ,use
Stateflow Editor > Add > Data/Event > Input from Simulink ®
Stateflow Editor > Add > Data/Event > Output to Simulink ®

The user then will need to fill in the data in the user interface provided, that is, provide the
name of the data variable, data type, scope, and so on. Then, Stateflow adds input and output
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ports for each “Input from Simulink ” and “Output to Simulink ” data definitions. The
port numbers are assigned in the order they are created, but can be changed by explicitly
specifying the port number in the definition menu.
Step 2: States, their hierarchy and decomposition. How many states are needed,
their hierarchy in terms of super-states and sub-states (parent-child relationship), and
whether they are exclusive (OR-states) or parallel (AND-states, concurrent) should be
decided. Consider the operation of your control logic or process model, and decide on the
modes of operation. In general, each mode of operation is assigned a state (Figure A.36). In
a state hierarchy, among the collection of OR states, only one of them can be active at a given
time, whereas multiple AND states can be active concurrently (although they are executed
still sequentially). The order of the sequential execution of parallel states (AND states)
can be left to default or specified by the designer. In the SF editor, exclusive (OR) states
are displayed with solid line rectangles, whereas parallel (AND) states are displayed with
dotted line rectangles. In the order to define the states as parallel in a hierarchy, right-click
the mouse inside the super-state where the parallel states will be defined, then select

Decomposition > Parallel (AND)