Page 7 - MMLP7AP Rev 1.0 Power Sequence _160307_Neat

1. AD19V MMLP7AP Rev 1.0 Power Sequence 24MHz

DC_ IN +V3.3A_DSW 2. PWR_BT 6. +V3.3A
LDO
-PANSHW
+V3.3A_RTC +VCCCORE
+V3.3A_DSW +VCCGT
+V3.3A PWRBTN# +VCCIO
TPS5331 TPS5331 IT RSMRST# 5. +VCCSA

PCH_SLP_S4#
4.
3. +5VSB_PG +V3.3A 8773FN PCH_SLP_S3# +VCCST_CPU
+VCCPLL_OC
+V3.3S
VREF +V_VDDQ_VR
+V5A +V3.3A_RTC
PCH_SLP_S4# 7. +V3.3A
PJ4N3K +V3.3S
DDR15_EN TPS53319 +V_VDDQ_VR +V1.8A
9. 8 DDR_VR_PWRGD +V1.00A
+V1.05S_PWRGD
TPS53318 PCH_SLP_S3# Haswell
10.
. +V1.05S CPU
+V5A +V5S +V1.05S_VCCST
SM3317 DDR_VR_PWRGD
PJ4N3K +V3.3S PJ4N3KX2 ATXPWOK ALL_SYS_PWRGD
+V3.3A SM3317 +V1.05S_PWRGD 11.
+V1.5S_PWRGD
+V1.05S_VCCST NCT3720
+V1.5S 12.
V1.05S_PWRGD PJ4N3K H_VCCST_PWRGD

H_VR_ENABLE 14. 13. H_VR_ENABLE
EN PWM VRRDY DELAY_VR_PWRGOOD
+19V , +V5S NCP81110 15.
ALL_SYS_PWRGD SN74LVC1G17 PM_PCH_PWROK
Notes : NCP81110 ramps to Vboot and hold SYS_PWROK
at Vboot until it receives a new SVID SN74LVC1G17
(See page NCP81110 Timing Diagram of Start Up) 16.
17. CK_LPC_24M_0
80H PCIE M.2 WGI219 NCT5532 PLT_RST#
18.
H_VR_ENABLE EN PWM VRRDY 19. SVID
+19V , +V5S NCP8111 +VCC_CORE
Dept : #41B研發服務部 By: Engineering