Page 47 - Z270X-Gaming 7 Rev 1.0 Introduction -170113
P. 47

KBL Timing Diagram for G3 to S0/M0 [Non-Deep Sx Platform]/3





    IMVP VR_ON

  CPU SVID BUS                                                                                                                  SetVID            SetVID

    SYS_PWROK

     SUS_STAT#

       PLTRST#                                  N_-PFMRST

                                                  VCORE
              VCC

          VCCGT

   THERMTRIP#                             Rises along with VccST
                                                  Soft    MAC     ME FW
      SPI Signals                                 Strap   PHY     Partly   Clock                                                       ME and BIOS
                                                  Reads   Config   read      Init                                                      activity will continue….

   DDR_RESET#


























   P.47                 Dept : #41B 研發服務部                      By : Engineering
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