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358 Fundamentals of Computers NPP
L-2 Cache (External Cache) L-2 Ho$e (~mhar Ho$e)
When the cache memory is put as a separate O~ Ho$e _o_moar H$mo AbJ go bJm`m OmVm h¡ Vmo Bgo
unit from CPU chip, this is called L-2 (Level-2) ~mhar Ho$e `m L-2 Ho$e H$hVo h¢Ÿ& Bgo _Xa~moS>© na CPU
cache or external cache. It is placed in between
the CPU and main memory on the motherboard. d _oZ _o_moar Ho$ _Ü` bJm`m OmVm h¡& {ZåZ {MÌ go `h
The following diagram illustrates it: ñnîQ> h¡:
L2 Cache
Cache
Memory
CPU
Main
Memory
The access time of L-2 cache is very low as BgH$m EŠgog Q>mB©_ _oZ _o_moar go ~hþV H$_ hmoVm
compared to main memory. But it is slower as h¡Ÿ& naÝVw `h L-1 Ho$e go Yr_r hmoVr h¡ Ÿ& 80386 Am¡a
compared to L-1 cache. The microprocessors
80386 and onward provide on chip support BgHo$ ~mX Ho$ àmogoga AnZr {Mn Ho$ D$na Amdí`H$
cache logic. Vm{H©$H$ n[anW àXmZ H$aVo h¢, Omo Ho$e H$mo MbZo _| _XX
H$aVo h¢Ÿ&
Cache Operation: Most frequently needed Ho$e {H«$`m: O¡gm {H$ h_ ~mV H$a MwHo$ h¢, AË`mdí`H$
data and Instructions are kept in cache memory. àmoJ«m_ d S>mQ>m Ho$e _o_moar _| aIm OmVm h¡ Ÿ& g~go nhbo
Therefore CPU first tries to find the data from CPU Ho$e _o_moar go OmZH$mar àmßV H$aZo H$s H$mo{ee
cache, if it is found then it is accessed from fast H$aVm h¡ Ÿ& AJa `hm± OmZH$mar {_b JB© Vmo Bggo H$_
cache. Otherwise the required data is accessed
from slow main memory, and this data and the EŠgog Q>mB©_ _| àmßV H$a boJmŸ& AJa `hm§ Zht {_br Vmo
whole block containing this data is transferred Yr_r _oZ _o_moar go àmßV H$aoJm Ÿ& BgHo$ níMmV² EH$ nyam
to cache. Thus, next time any word within this IÊS> _oZ _o_moar go Ho$e _| ^oOm OmEJm Ÿ& AJbr ~ma Bg
block will be available in cache memory. IÊS> _| go {H$gr ^r eãX H$m H$m_ n‹S>Vm h¡ Vmo `h Ho$e
_| CnbãY hmoJmŸ&
Cache Hit: When the CPU makes request Ho$e {hQ>: O~ CPU {H$gr eãX H$mo Ho$e _| go àmßV
for a particular word in cache memory and it is H$aZm MmhVm h¡ Am¡a dh eãX dhm± {_b OmVm h¡ Vmo Bg
found there, then this occurence is said to be KQ>Zm H$mo Ho$e {hQ> H$hVo h¢ Ÿ& `h EH$ AÀN>r KQ>Zm h¡ Ÿ&
cache hit. The caching system is aimed to pro- AÀN>m Ho$qeJ {gñQ>_ dh hmoVm h¡ Ohm± Ho$e {hQ> Á`mXm go
duce as many hits as possible.
Á`mXm hmoVo h¢ Ÿ&
Cache Miss: When a CPU makes reference Ho$e {_g: O~ CPU Ho$e _o_moar go H$moB© eãX àmßV
for a word in cache and it is not found, then this H$aZm MmhVm h¡ Am¡a dh eãX dhm± Zht {_bVm h¡ Vmo Bg
occurrence is called cache miss. This is an un-
fortunate event in the caching system, because KQ>Zm H$mo Ho$e {_g H$hVo h¢ & `h EH$ Xw^m©½`nyU© KQ>Zm h¡
