Page 4 - FUNDAMENTALS OF COMPUTER
P. 4
UNIT - 3
Number System: Decimal, Binary, Octal, Hexadecimal, Conversions from one base to another
base. Codes: ASCII Code, EBCDIC Code, Gray Code, Boolean Algebra, De-morgan's theorem,
Binary Arithmetic: Addition, Subtraction, Multiplication & Division, Unsigned binary numbers,
Signed Magnitude Numbers, 1’s Complement & 2's Complement Representation of Numbers, 2's
Complement Arithmetic, Boolean Functions & Truth Tables, SOP, POS form, Minterms/
Maxterms, Simplification of Logic Circuits using Boolean Algebra and Karnaugh Maps, Logic
Gates: AND, OR, NOT, NAND, NOR, X-OR and X-NOR Gates, their Symbols and Truth Tables,
Circuit Design With Gates: Adder/Subtractor Circuit.
Zå~a {gñQ>‘… S>ogr‘b, ~m¶Zar, Am°³Q>b, ho³gmS>ogr‘b, EH$ ~og go Xÿgao ~og ‘| H$ÝdO©Ýg& H$moS²>g… ASCII H$moS>,
EBCDIC H$moS>, J«o H$moS>& ~y{b¶Z EëOo~«m, {S>-‘m°J©Z H$s ϶moa‘, ~m¶Zar AW©‘o{Q>H$… Omo‹S>, KQ>md, JwUm VWm ^mJ,
AZgmBÝS> ~m¶Zar Zå~g©, gmBÝS> ‘¡½ZrQ²>¶yS> Zå~g©, 1’s H$m°åßbr‘|Q> VWm 2's H$m°åßbr‘|Q> AW©‘o{Q>H$& ~y{b¶Z ’§$³eÝg
VWm Q®>W Q>o~ëg, SOP, POS ’$m°‘©, {‘ZQ>åg©/‘¡³gQ>åg©, ~y{b¶Z EëOo~«m VWm H$aZm°’$ ‘¡ßg H$m Cn¶moJ H$aHo$ bm°{OH$
g{H©$Q²>g H$m gabrH$aU& bm°{OH$ JoQ²>g… AND, OR, NOT, NAND, NOR, X-OR VWm X-NOR JoQ²>g, CZHo$ {MÝh
VWm Q®>W Q>o~ëg, JoQ²>g Ho$ gmW g{H©$Q> {S>OmBZ… ES>a/gãQ´>o³Q>a g{H©$Q>&
UNIT - 4 NPP
Memory cell, Primary Memory: RAM, Static and Dynamic RAM, ROM, PROM, EPROM,
EEPROM, Cache Memory, Secondary Memory and its Types, Virtual Memory Concept, Memory
Accessing Method: Serial and Random Access. Data Bus, Control Bus & Address Bus. Word
Length of a Computer, Memory Addressing Capability of CPU, Processing Speed of a Computer,
Microprocessors, Single Chip Microcomputers (Microcontrollers).
‘o‘moar gob, àm¶‘ar ‘o‘moar… RAM, ñQ>o{Q>H$ VWm S>m¶Zm{‘H$ RAM, ROM, PROM, EPROM, EEPROM, H¡$e
‘o‘moar, goH$ÊS>ar ‘o‘moar VWm BgHo$ àH$ma, dMw©Ab ‘mo‘moar H$s AdYmaUm, ‘o‘moar E³goqgJ ‘oWS²>g… gr[a¶b VWm a¡ÊS>‘
E³gog& S>mQ>m ~g, H$ÊQ´>mob ~g VWm ES´>og ~g& EH$ H$å߶yQ>a H$s dS>© b¢S>, EH$ CPU H$s ‘o‘moar ES´>oqgJ j‘Vm, EH$
H$å߶yQ>a H$s àmogoqgJ ñnrS>, ‘mBH«$mo àmogoga, qgJb {Mn ‘mBH«$moH$å߶yQ>g© (‘mBH«$mo H$ÊQ´>moba)
UNIT - 5
General architecture of a CPU, instruction format, and data transfer instructions, data
manipulation instructions and program control instructions. Types of CPU organization:
accumulator based machine, stack based machine and general-purpose register based machine,
addressing modes, data transfer schemes: (i) programmed data transfer: synchronous,
asynchronous, and interrupt driven data transfer (ii) direct memory access data transfer: Cycle
stealing, block transfer and burst mode of data transfer.
EH$ CPU H$r gm‘mݶ g§aMZm, BÝñQ´>³eZ ’$m°‘}Q> VWm S>mQ>m Q´>mÝg’$a BÝñQ´>³eÝg, S>mQ>m ‘oZrnwboeZ BÝñQ´>³eÝg VWm
àmoJ«m‘ H$ÊQ´>mob BÝñQ´>³eÝg& CPU Am°J}ZmBOoeZ Ho$ àH$ma… E³¶y‘wboQ>a ~oñS> ‘erZ, ñQ>¡H$ ~oñS> ‘erZ VWm OZab-
nanO a{OñQ>a ~oñS> ‘erZ, ES´>oqgJ ‘moS²>g, S>mQ>m Q´>mÝg’$a ñH$såg… (i) àmoJ«måS> S>mQ>m Q´>mÝg’$a… {gÝH«$moZg, E{gÝH«$moZg
VWm BÝQ>aßQ> S´>mBda S>mQ>m Q´>mÝg’$a (ii) S>m¶ao³Q> ‘o‘moar E³gog S>mQ>m Q´>mÝg’$a… gm¶H$b ñQ>rqbJ ãbm°H$ Q´>mÝg’$a VWm
S>mQ>m Q´>mÝg’$a H$m ~ñQ>© ‘moS>&
