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Efficient Post-silicon Debug Platforms for Future Many-core Systems
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Mr. Sidhartha Rout*
Email: sidharthas@iiitd.ac.in
Tremendous advancements in CMOS desired performance, power and reliability (Complementary Metal Oxide in the contemporary designs, interconnects Semiconductor) manufacturingarereinforcedwithadditionalhardwareand technology have led to rapid growth in the
semiconductor industry. As the computation is moving towards exascale era, more number of processing cores (alternatively known as processing elements (PE)) with heterogeneous nature (CPU/GPU/accelerators) are getting embedded on a system-on-chip (SoC). The growing demand for high-performance and increased functionalities would further proliferate this trend on future SoCs. Such a system requires an efficient interconnected infrastructure to establish parallel and reliable communication among the cores. Modern complex interconnect systems are augmented with new features to serve the increasing number of on-chip PEs. To achieve the
* Mr. Sidhartha Rout, PhD Scholar from Indraprastha Institute of Information Technology, Delhi, is pursuing his research on “Design for Debug for Future Many-Core Systems”. His popular science story entitled “Efficient Post-Silicon Debug Platforms for Future Many-Core Systems” has been selected for AWSAR Award.
pipeline stages. Since the interconnect module has gained multi-fold design complexity, it is not possible to capture all the functional bugs at the pre-silicon verification phase. The escaped bugs on interconnect unit can bring in multiple data communication faults like deadlock, packet drop, which can lead to complete system failure. So, strong post- silicon debug (alternatively known as post- silicon validation) should be performed on early prototypes of interconnect chips to make the design fault free. The validation process is also expected to be of high speed to meet the tight time-to-market scenario. A post-silicon validation method helps to detect the bugs by increasing the observability and controllability
