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202 || AWSAR Awarded Popular Science Stories - 2019
of the internal nodes of a fabricated system. During validation process, traces of multiple system internal signals are collected and analyzed for the detection of any existing fault. Design-for-debug (DfD) structures are used to record and store the traces. Collected traces are stored in an on-chip DfD structure called,
trace buffer. These traces are later transferred to the off-chip debug analyzer for fault analysis. Fig. 1 illustrates the debug platform for a multi- core system. From the Fig., it can be seen that trace buffer, trigger unit, interconnection fabric (trace bus), and the interface ports are the major components of the debug platform.
 Fig. 1. Trace-based interconnect debug platform. The many-core system with its interconnect is considered as the Circuit Under Debug (CUD) over here. A DfD structure has been embedded and an Off-chip Debug Analyzer is instrumented for the post-silicon validation of the CUD.
The objective of a debug
engineer is to collect as many
traces as possible for as
many signals. This way the
visibility of internal states can
be maximized during analysis
phase. More traces provide
more pointers regarding the
presence of a particular fault
and help in finding its root-
cause. But high volume of
traces needs a large size trace
buffer to be stored, which would
increase associated area and
power overhead. It also leads
to longer trace transfer time for exporting enlarged traces to the debug analyzer. The DfD structures are not reused after the validation phase. This further discourages the idea of having a large size trace buffer. But, small and fixed-size on-chip trace buffer limits the amount of trace collected. This motivates us to
come up with an efficient post- silicon debug platform that can optimally use the available small trace buffer to provide enough internal observability of the system and also can perform high-speed trace transfer. We have proposed wireless enabled debug platform with augmented redundant trace elimination (RTE) mechanism that can optimally utilize the existing trace buffer space and can provide high trace transfer capability.
The proposed RTE mechanism reduces the total trace amount. Traces of internal signals are captured periodically, once after each snapshot interval. If the state of a particular signal does not change frequently, then with a small snapshot interval, multiple redundant traces get generated for the
   The validation process is also expected to be of high speed to meet the tight time- to-market scenario. A post- silicon validation method helps to detect the bugs by increasing the observability and controllability of the internal nodes of a fabricated system.
  











































































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