Page 74 - Mechatronics with Experiments

60 MECHATRONICS
signals can be a little different from one cycle to the next due to the variations in the A/D
conversion. The period for which the control signal is held constant is

T = T − T + T (2.43)
u c k c k+1
where T = (t + t + t + t ) and T = (t + t + t + t ) are the total time spent in
2
1
4 k
3
2
1
4 k+1
3
c k c k+1
the foreground program execution during sampling interval k, and k + 1, respectively. Due
to the variations in the A/D conversion time, t , the effective update period T for control
2
u
action may vary from one sample to the next. Hence, the control system may not have
a truly constant sampling period. This is a potential problem which may or may not be
significant depending on the application. However, this implementation minimizes the time
delay between the measured sensor signal and the corresponding control action since the
control action is updated as soon as it is available. If minimizing the time delay associated
with the digital controller is more important than maintaining a truly constant sampling
frequency, this implementation is appropriate to use. Another implementation is shown on
the right side of Figure 2.10. The sequence of operations in the foreground program is a
little different:
1. send the control action calculated from the previous period to D/A,
2. determine the desired response (sample from A/D if necessary),
3. A/D sample of the sensor signal,
4. calculate the control action and keep it for the next sampling period,
5. return to the background program.
The difference is that sending out the control signal to the D/A converter is the first
thing done every sampling period. The control signal sent out is the signal calculated
during the previous sampling period. The signal calculated during this period is sent
to the D/A converter at the beginning of the next sampling period. The advantage of this
implementation is that the control signal is updated in a truly fixed sampling period. As long
as the sampling period is long enough to complete the foreground program every sampling
period, the update of the control signal is done at a fixed frequency. The disadvantage is that
the effective time delay associated with digital processing of the control signal is longer
than the previous implementation. The time delay is at most one sampling period long. If
the sampling frequency is much larger than the bandwidth of the closed loop system, that
should not be a serious problem. As the sampling frequency gets closer to the bandwidth
of the closed loop system, the larger time delay in the second implementation compared to
the first implementation may have serious performance degrading consequences.

2.2.6 Filtering and Bandwidth Issues

The sampling theorem requires that the sampling frequency must be at least twice the
highest frequency content of the signal being sampled. However, real-world signals always
have some level of noise in them. The frequency of the noise component of the signal is
generally very high. Therefore, it would not be practical to use very fast sampling rates in
order to handle the noise and avoid the aliasing problem. Furthermore, the noise content
of the signal is not something we would like to capture. It is an unwanted component.
Therefore, signals are generally passed through anti-aliasing filters before sampling at the
A/D circuit. This is called pre-filtering. The purpose of anti-aliasing filters is to attenuate
the high frequency noise components, and pass the low frequency components of the signal
(Figure 2.11). The bandwidth of the anti-aliasing filter (also called the noise filter) should
be such that it should not pass much of the signal beyond 1∕2 of the sampling frequency. An