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ROHM’S FOURTH-GENERATION SiC MOSFET IMPROVES THE TRADEOFF RELATIONSHIP BETWEEN SHORT-CIRCUIT RUGGEDNESS AND ON-STATE RESISTANCE.
The reduced Ron is a result of a smaller unit cell pitch, an improved MOS interface, wafer backside grinding, and other performance-enhancing design strategies. The results of these strategies have not led to a compromise of the short- circuit withstand time (SCWT). This is important, as typical reductions in Ron lead to increases of saturation current and higher heat dissipation on a chip during a short-circuit event, with commensurately faster junction temperature rise and shorter SCWT.
Reduced Crss is another advantage of the fourth genera- tion of this specific SiC MOSFET technology. This has led to increased dV/dt speed and lower Eon/Eoff. The device also exhibits a lower Crss/Ciss ratio, with lower Err and lower Vgs surge compared with third-generation devices. Along with minimizing the risk of parasitic turn-on, the improved design
With better switching loss performance, a device can operate at a higher frequency without exceeding the heat-dissipation limits.
and cell structure of the newer-generation SiC MOSFETs demonstrate a switching loss reduction of about 50% com- pared with previous-generation devices.
Switching losses happen during the transition of a device from blocking (off-state) to conducting (on-state) and vice versa. Reduced switching loss is significant, as switching losses directly contribute to device efficiency and heat buildup dur- ing use. With better switching loss performance, a device can operate at a higher frequency without exceeding the heat-dissipation limits. This additional margin often opens up possibilities to reduce inductor and capacitor component sizes and leads to a more compact power-converter system.
SiC SDIP module provides optimal
integrated package
Improved chip design for greater power efficiency requires optimal device packages to maximize switching performance and reduce the component footprint. Discrete packages with added driver-source connections can help enable this, along with a skinny dual in-line package (SDIP) power module with compact size and flexible internal topologies.
For discrete products featuring separate Kelvin source pins, the source stray inductance on the main current path no lon- ger influences the effective gate voltage applied to
SWITCHING LOSS COMPARISON — FOURTH-GENERATION SiC MOSFET VERSUS THIRD-GENERATION SiC MOSFET
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Resources New Generation of SiC MOSFETs Geared Toward xEVs and Industrial Applications