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pair can be added.) There are no separate address lines in a serial bus. Serial buses are often set up for
point-to-point connection; no addressing is required in this case.
If addressing is required in a serial bus application, the address may be multiplexed with the data. What
this means is that the same line is used for both address and data at different times; if an address is
required, for example, the address might be sent first, one bit at a time, followed by the data. At its
simplest, the serial bus can be reduced to a single data line pair, used for data, control, and addressing.
Using modern materials such as fiber optics, very high transfer rates may be achieved. In general, control
is handled using a bus protocol that establishes agreement as to the meaning and timing of each signal
on the line among the components connected to the line. It is also possible to design a parallel bus that
multiplexes addresses and data on the same lines, as the PCI bus does, or multiplexes32-bit data on
sixteen data lines, for example. For example, the Pentium 4 multiplexes 128-bit data words to fit a 64-
bit data path on the Pentium system bus. To use a bus, the circuits that are connected to the bus must
agree on a bus protocol.
A bus protocol is simply a specification that spells out the meaning of each line and each signal on each
line for this purpose. Thus, a particular control line on a bus might be defined as a line that determines
if the bus is to be used for memory read or memory write. Both the CPU and memory would have to
agree, for example, that a ‘‘0’’ on that particular line means ‘‘memory read’’ and a ‘‘1’’ on the line means
‘‘memory write’’. The line might have a name like MREAD/MWRITE, where the bar over MWRITE means
that a ‘‘0’’ is the active state. The bar itself stands for ‘‘NOT’’.3 Buses are frequently notated on diagrams
using widened lines to indicate buses. Sometimes a number is also present on the diagram. The number
indicates the number of separate lines in the bus. Two alternative ways of notating buses in diagrams
are shown in Figure below.
41 Academic Year 2025/2026

