Page 156 - Programmable Logic Controllers, Fifth Edition

• Logix processors use a tag name, such as Pump_
Motor, instead of a timer number. • When input switch A is closed (true or set to 1), the
processor starts timer T4:0 timing and sets the EN
• This descriptive tag name makes it easier to know and TT bits to true or 1.
what function the timer serves in the control • This turns ON outputs B and C
system. • The accumulated value increases in one-second
• The time base is fixed at 0.001 s (1 ms). Therefore time base intervals.
there is no parameter field. • When the accumulated time equals the preset time
• The associated timer data (PRE, ACC, EN, TT, DN) (10 s), the DN bit is set to 1, output D is turned ON,
are found within the expanded timer structure. the TT bit is reset to 0 and output C is turned OFF.
The on-delay timer (TON) is the most commonly used • As long as input switch A remains closed the EN bit
timer. Figure 7-15 shows a PLC program that uses an on- is set to 1 and output B will be ON.
delay timer. The operation of the program can be sum- • If input switch A is opened at any time before or
marized as follows: after the timer has timed out, the accumulated time is
automatically reset to 0 and output B is turned OFF.
• The timer is activated by input switch A.
• This timer configuration is termed nonretentive
because any loss of continuity to the timer causes
the timer instruction to reset.
Timer ON DELAY (TON)
• This timing operation is that of an on-delay timer
Enable Bit (EN) 0
TON because output D is switched on 10 s after the switch
Instruction Timer Timing Bit (TT) 0
Done Bit (DN)
0
OFF has been actuated from the off to the on position.
Accumulating NO
Enable Bit (EN) 1 Figure 7-16 shows the timing diagram for the on-
TON Timer Timing Bit (TT) 1
Instruction Done Bit (DN) 0 delay timer’s control bits. The sequence of operation is
ON as follows:
Accumulating YES
Enable Bit (EN) 1 • The first true period of the timer rung shows the
Timed Out Timer Timing Bit (TT) 0
Accum = Preset Done Bit (DN) 1 timer timing to 4 s and then going false.
Accumulating NO • The timer resets, and both the timer-timing bit and
Enable Bit (EN) 0 the enable bit go false. The accumulated value also
Instruction OFF Timer Timing Bit (TT) 0
after timed out Done Bit (DN) 0 resets to 0.
Accumulating Reset • For the second true period input A remains true in
Table showing how each bit is eected during the program operation. excess of 10 s.

Input Ladder logic program Outputs
L1 L2
Input A TON
Input A TIMER ON DELAY Output B G
Timer T4:0 EN
Time base 1.0
Preset 10 DN
Accumulated 0 Output C R
T4:0 Output B

EN Output D Y
T4:0 Output C

TT
T4:0 Output D

DN
Figure 7-15 PLC on-delay timer program.

Programming Timers Chapter 7 137

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