Page 161 - Programmable Logic Controllers, Fifth Edition
P. 161

Input                    Ladder logic program                     Outputs
                          L1                SW                                                             L2
                                                         TOF
                             Switch                      TIMER OFF DELAY        EN
                                   SW                    Timer           T4:1                         OL
                                                         Preset            5   DN          M1
                                                         Accumulated       0
                                                                                                      OL
                                                         TOF
                                                         TIMER OFF DELAY        EN        M2
                                                         Timer           T4:2
                                                         Preset           10   DN                     OL
                                                         Accumulated       0              M3

                                                         TOF
                                                         TIMER OFF DELAY        EN
                                                         Timer           T4:3
                                                         Preset           15   DN
                                                         Accumulated       0
                                           T4:1/DN                              M1




                                           T4:2/DN                             M2



                                           T4:3/DN                             M3




                          Figure 7-22  Program for switching motors off at 5 s intervals.




                 •  Timer T4:2 times out 5 s later resetting its done bit   •  When limit switch LS1 is opened, the off-delay
                    to zero to de-energize motor M2.                      timer coil TD de-energizes and the time-delay
                 •  Timer T4:3 times out 5 s later resetting its done bit   period is started.
                    to zero to de-energize motor M3.
                                                                                 L1                        L2
                  Figure 7-23 shows a hardwired off-delay timer relay
               circuit with both instantaneous and timed contacts. The               LS1
               operation of the circuit can be summarized as follows:                          5 s  TD
                 •  When power is first applied (limit switch LS open),              TD-1              OL
                    motor starter coil M1 is energized and the green                              M1
                    pilot light is on.
                 •  At the same time, motor starter coil M2 is de-                   TD-2              OL
                    energized, and the red pilot light is off.                                    M2
                 •  When limit switch LS closes, off-delay timer coil
                    TD energizes.                                                    TD-3
                 •  As a result, timed contact TD-1 opens to de-                                   G
                    energize motor starter coil M1, timed contact TD-2
                    closes to energize motor starter coil M2, instanta-              TD-4
                    neous contact TD-3 opens to switch the green light                             R
                    off, and instantaneous contact TD-4 closes to switch
                    the red light on. The circuit  remains in this state as   Figure 7-23  Hardwired off-delay timer relay circuit with
                    long as limit switch LS1 is closed.              both instantaneous and timed contacts.



               142        Chapter 7  Programming Timers







          pet73842_ch07_131-155.indd   142                                                                              05/11/15   4:21 PM
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