Page 89 - Programmable Logic Controllers, Fifth Edition

Starts
Stops Relay schematic Ladder logic program Gate logic
PB1 Stops Starts
PB3 PB4 Motor C D A M Starts
M
C D A PB3 PB4 PB1 Motor A
PB2 B Stops
B
C M
B PB2
Motor M D

M Motor
Example 4-9 A motor control circuit with two start/stop buttons. When either start button is depressed, the motor runs. By use of
a seal-in contact, it continues to run when the start button is released. Either stop button stops the motor when it is depressed.

4.7 Programming Word Level Logic
Instructions MOV MVM AND OR XOR NOT CLR

Most PLCs provide word-level logic instructions as Compare Compute/Math Move/Logical File/Misc
part of their instruction set. Table 4-1 shows how to
select the correct word logic instruction for different Input A AND
situations. BITWISE AND
Figure 4-24 illustrates the operation of the AND in- Source A B3:5
struction to perform a word-level AND operation using 1100110011001100 B3:7
Source B
the bits in the two source addresses. This instruction tells 1111111100000000
the processor to perform an AND operation on B3:5 and Destination B3:10
1100110000000000
B3:7 and to store the result in destination B3:10 when
input device A is true. The destination bits are a result of Source A 110011001100110 0
the logical AND operation. B3:5
Figure 4-25 illustrates the operation of a word-level Source B 1111111100000000
OR instruction, which ORs the data in Source A, bit by B3:7
bit, with the data in Source B and stores the result at the Destination 1100110000000000
destination address. The address of Source A is B3:1, B3:10
the address of Source B is B3:2, and the destination Figure 4-24 Word-level AND instruction.
address is B3:20. The instruction may be programmed
conditionally, with input instruction(s) preceding it, or
unconditionally, as shown, without any input instruc- MOV MVM AND OR XOR NOT CLR
tions preceding it.
Figure 4-26 illustrates the operation of a word-level Compare Compute/Math Move/Logical File/Misc
XOR instruction. In this example, data from input I:1.0
are compared, bit by bit, with data from input I:3.0. OR
BITWISE INCLUS OR
Source A B3:1

Table 4-1 Selecting Logic Instructions Source B B3:2
Destination B3:20
. . . use this
If you want to . . . instruction.
Source A 1 10011001100110 0
Know when matching bits in two different AND B3:1
words are both ON
Know when one or both matching bits in two OR Source B 1 11111110000000 0
different words are ON B3:2
Know when one or the other bit of matching XOR Destination
bits in two different words is ON B3:20 1 11111111100110 0
Reverse the state of bits in a word NOT
Figure 4-25 Word-level OR instruction.

70 Chapter 4 Fundamentals of Logic

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