Page 220 - Programmable Logic Controllers, Fifth Edition - Mobile version

program may require certain calculations to be executed
at a repeatable time interval for accuracy. These calcula- the STD and STE instructions and can be summarized
as follows:
tions can be accomplished by placing this programming • In this program, STI is assumed to be in effect.
in the selectable timed-interrupt file. This instruction can
also be used for process applications that require periodic • The STD and STE instructions in rungs 6 and 12
lubrication. are included in the ladder program to avoid having
The immediate input and immediate output instruc- STI subroutine execution at any point in rungs 7
tions are often located in a selectable timed interrupt file, through 11.
so that a particular section of program is updated on a • The STD instruction (rung 6) resets the STI enable
timed basis. This process could be done on a high-speed bit, and the STE instruction (rung 12) sets the
line, when items on the line are being examined and the enable bit again.
rate at which they pass the sensor is faster than the scan • The SELECTABLE TIMED ENABLE instruction
time of the program. In this way, the item can be scanned of rung 0 is triggered by the first pass bit status file
multiple times during the program scan, and the appro- S:1/15. The first pass bit, S:1/15, will only be true
priate action may be taken before the end of the scan. for the first scan through ladder file 3 when the PLC
The selectable timed disable (STD) instruction processor goes into the run mode. On subsequent
is generally paired with the selectable timed enable scans, S:1/15 will not be true. This ensures that the
(STE) instruction to create zones in which STI inter- STI function is initialized after each power cycle.
rupts cannot occur. Figure 9-26 illustrates the use of
9.9 Fault Routine

Program file 3 S:1 STE Allen-Bradley SLC 500 controllers allow you to designate
0 SELECTABLE TIMED ENABLE a subroutine file as a fault routine. If used, it determines
15
how the processor responds to a programming error. The
1 program file assigned as the fault routine is determined
by the value stored in word S:29 of the status file. Enter-
2
ing a 0 in word S:29 disables the fault routine.
3 There are two kinds of major faults that result in a
4 processor fault: recoverable and nonrecoverable faults.
When the processor detects a major fault, it looks for a
5 fault routine. If a fault routine exists, it is executed; if one
STD
6 SELECTABLE TIMED DISABLE does not exist, the processor shuts down. When there is a
fault routine, and the fault is recoverable, the fault routine
7 is executed. If the fault is nonrecoverable, the fault rou-
tine is scanned once and shuts down. Either way, the fault
8
STI execution routine allows for an orderly shutdown.
will not occur 9
between STD
and STE. 10 9.10 Temporary End Instruction

11
The temporary end (TND) instruction is an output
STE instruction used to progressively debug a program or
12 SELECTABLE TIMED ENABLE conditionally omit the balance of your current program
file or subroutines. When rung conditions are true, this
13 instruction stops the program scan, updates the I/O, and
14 resumes scanning at rung 0 of the main program file.
Figure 9-27 illustrates the use of the TND instruction
15
in troubleshooting a program. The TND instruction lets
16 your program run only up to this instruction. You can

17 End move it progressively through your program as you debug
each new section. You can program the TND instruction
Figure 9-26 Selectable timed disable (STD) and selectable unconditionally, or you can condition its rung according
timed enable (STE) instructions. to your debugging needs.

Program Control Instructions Chapter 9 201

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