Page 265 - Programmable Logic Controllers, Fifth Edition - Mobile version

L1 Input SW Ladder logic program L1 Input SW Ladder logic program
FAL FAL
SW FILE ARITH/LOGICAL EN SW FILE ARITH/LOGICAL EN
Control R6:8 DN Control R6:7 DN
Length 4 Length 4
Position 0 ER Position 1 ER
Mode All Mode Incremental
Destination #N7:500 Destination F8:200
Expression Expression
#N7:330 N7:23 #F8:20 / #F8:100
*
#F8:20 #F8:100 F8:200
#N7:330 N7:23 #N7:500
F8:20 100 ÷ F8:100 1000 = F8:200 0.1
N7:330 20 * N7:23 100 = N7:500 2000 25 2
240 24000 1.33 1.5
–78 –7800
N7:333 321 = N7:503 32100 F8:23 586 F8:103 3
Figure 11-26 SLC 500 file multiply function of the FAL Figure 11-27 SLC 500 file divide function of the FAL
instruction. instruction.

The program of Figure 11-26 is an example of the file The program of Figure 11-27 is an example of the file
multiply function of the FAL instruction. The operation of divide function of the FAL instruction. The operation of
the logic rung can be summarized as follows: the logic rung can be summarized as follows:
• When input switch SW is closed the rung goes • When input switch SW is closed the rung goes true
true and the data in file address N7:330 is multi- and the data in file address F8:20 is divided by the
plied by the data in element address N7:23, with data in file address F8:100, with the result stored in
the result stored at the destination file address element address F8:200.
N7:500. • The mode is Incremental, so the instruction operates
• The rate per scan is set at All, so the instruction on one set of elements for each false-to-true transi-
goes to completion in one scan. tion of the instruction.

246 Chapter 11 Math Instructions

pet73842_ch11_234-251.indd 246 03/11/15 4:08 PM