Page 292 - Programmable Logic Controllers, Fifth Edition - Mobile version

The SLC 500 FIFO load (FFL) instruction is shown
in Figure 12-34. The parameters that are required to be
entered in the instruction block are summarized as follows:
Source—Word address from which the data are en-
tered into the FIFO file.
FIFO—Address of the file in which the data are en-
tered. The address must start with a # sign.
Control—R data-table type and is the file address of
the control structure. The status bits, stack length, and
position are stored in this element.
Length—File length in words. Specifies the maxi-
Figure 12-33 Barcode reader. mum number of words in the stack.
Source: Courtesy Keyence Canada Inc. Position—Is the next available location where the
instruction loads data into the stack. The first address
used for tracking parts through an assembly line, where in the stack is position 0. As each word is entered into
parts are represented by values that have a part number or the stack, the position counter, on both the FFL and
an assembly code. Figure 12-33 shows a barcode reader FFU, will increment up by one. The stack is consid-
used for reading printed barcode data on boxes. ered full when the position value equals the length.
A bit shift register operates synchronously; because The status bits of the control word are the enable
for every bit shifted in, one is shifted out. Data entered in (EN), the done (DN), and the empty (EM) bits. Their
a bit shift register must be shifted the length of the register functions can be summarized as follows:
(one position per shift pulse) before they are available to - Enable Bit (EN)—The enable bit follows the instruc-
shift out. tions status and is set to 1 when the instruction is true.
A FIFO function operates asynchronously. Rather than - Done Bit (DN)—The done bit is set to 1when the in-
shifting bits of information within a word it shifts the data struction’s position equals the length. When the done
from a complete word into a file or stack. Unlike the bit bit is set, the FIFO is full and does not accept any
shift register, two separate shift pulses are required: one more data. Also the data in the FIFO file are not over-
to shift data into the file (load) and one to shift data out of written when the instruction goes from false to true.
the file (unload). These two shift pulses operate indepen- - Empty Bit (EM)—The empty bit is set to 1 when
dently (asynchronously) of each other. Data loaded in a all the data have been unloaded from the FIFO file.
FIFO can be immediately available for unload, regardless
of length. Figure 12-35 shows the SLC 500 FIFO unload (FFU)
The FFL and FFU instruction are used in pairs. The instruction. The following parameters need to be entered
FFL loads logic words into a user-created file called in the SLC 500 FFU instruction:
a FIFO stack. The FFU instruction is used to unload FIFO—Address of the file in which the data are
the words from the FIFO stack, in the same order as the entered. The address must start with a # sign. When
words were entered. The first word entered is the first paired with an FFL instruction, this address is the
word out. same as the address for the FFL.

BSL BSR SQC SQL SQO FFL FFU LFL LFU BSL BSR SQC SQL SQO FFL FFU LFL LFU
File/Misc File Shift / Sequencer Program Control File/Misc File Shift / Sequencer Program Control

FFL FFU
FIFO LOAD EN FIFO UNLOAD EU
Source FIFO
FIFO DN Destination DN
Control Control
Length EM Length EM
Position Position

Figure 12-34 SLC 500 FIFO load (FFL) instruction. Figure 12-35 SLC 500 FIFO unload (FFU) instruction.

Sequencer and Shift Register Instructions Chapter 12 273

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