Page 38 - Epistle 2018 ISSUE 1

TECH TALK

As the demand for faster devices increases for growing

industrial applications, scaling beyond 7nm is now

indispensable. According to the ITRS v2.0, the technology

nodes 2.5nm and 1.5nm are to be reached by 2027 and

2030 respectively to fulfill the requirements of

semiconductor industries. There are many challenges to

scale below sub-10nm due to process complexities and

increasing costs. The aggressive scaling down of transistors

increases the short channel effects and leakage current. As

the source and drain of the MOSFET are getting closer, there

is increase in lateral electric field and thereby loses gate

control over the channel. For these reasons, it is very difficult

to scale down the bulk MOSFETs beyond 20 nm.

The FinFET devices are emerged as innovative

technology to reduce the short channel effects and improve

the gate voltage controllability which could extend scaling

upto 7nm technology. At sub-7nm technology, the channel

size has a similar size as the depletion layer and quantum

phenomena such as tunneling become increasingly

probable. The Gate-All-Around (GAA) FET with better

performance and reduced leakage may extend upto

4nm/3nm technology node. Beyond 3nm technology node,

the chip makers need an innovative solution to modify the

existing technology without changing the conventional

process steps.