Page 13 - MZBAYAP Rev 1.2 Introduction _160119 _Neat

2-5. Power Management
• ACPI System States support (S0, S0i1, S0i2, S0i3, S3, S4, S5)
• Processor Core/Package States support (C0 – C7)
Note: The Bay Trail-D SoC supports C0-C1 only.
• SoC Graphics Adapter States support D0 – D3.
• Support Link Power Management (LPM)
• Thermal throttling
• Dynamic I/O power reductions (disabling sense amps on input buffers, tri-stating

output buffers)
• Active power down of Display links
2-6. PCI Express
The SoC has four PCI Express* lanes and up to four PCI Express root ports, each supporting
the PCI Express Base specification Rev 2.0 at a maximum of 5 Gbit/s data transfer rates.The root
ports configurations are flexible and can be configured to be (4) x1, (2) x2’s, (1) x2 plus (2) x1’s,
and (1) x4.
2-7. SATA
• Two (2) SATA Revision 2.0 ports (eSATA capable)

• Legacy IDE (including IRQ)/Native IDE/AHCI appearance to OS
• Partial/Slumber power management modes with wake
• Capable of 3 Gbit/s transfer rate
• Supports RunTime D3
2-8. USB xHCI Controller
• Supports USB 3.0/2.0/1.1
• Implements xHCI software host controller interface
• One USB 3.0 Super Speed (SS) port
• Four ports multiplexed with EHCI controller that are High Speed/Full Speed (HS/FS)

Dept : #41B研發服務部 By: Engineering