Page 20 - vinafix.com_Compal AAL15 LA-D071P r1.0

5 4 3 2 1

<7> DDR_A_DQS#[0..7]
Reverse Type
<7> DDR_A_D[0..63] +DDR_VREF_A_DQ0 +1.35V_MEM +1.35V_MEM
JDIMM1
<7> DDR_A_DQS[0..7] 1 2
VSS
<7> DDR_A_MA[0..15] 3 VREF_DQ DQ4 4 DDR_A_D1
VSS
DDR_A_D4 5 DQ0 DQ5 6 DDR_A_D0
1 DDR_A_D5 7 DQ1 VSS 8
9 10 DDR_A_DQS#0
@
D CD5 11 VSS DQS0# 12 DDR_A_DQS0 D
Note: 2 13 DM0 DQS0 14
VSS
VSS
Check voltage tolerance of DDR_A_D3 15 DQ2 DQ6 16 DDR_A_D6 +1.35V_MEM
VREF_DQ at the DIMM socket DDR_A_D7 17 DQ3 DQ7 18 DDR_A_D2
2.2U_0402_6.3V6M
19 20
DDR_A_D9 21 VSS VSS 22 DDR_A_D13
Layout Note: DDR_A_D8 23 25 DQ8 DQ12 24 26 DDR_A_D12 1
DQ9
DQ13
Place near JDIMM1 DDR_A_DQS#1 27 VSS VSS 28
DQS1#
DM1
DDR_A_DQS1 29 DQS1 RESET# 30 DDR_DRAMRST#_R 470_0402_1% RD2
31 32
VSS
DDR_A_D10 33 VSS DQ14 34 DDR_A_D15 2
DQ10
DDR_A_D11 35 DQ11 DQ15 36 DDR_A_D14 RD29
37 38 0_0402_5%
DDR_A_D35 39 VSS VSS 40 DDR_A_D32 1 @ 2 DDR_DRAMRST#
+1.35V_MEM DDR_A_D37 41 DQ16 DQ20 42 DDR_A_D36 1 0.1U_0402_25V6 CD6 ESD@ <21> DDR_DRAMRST#_R DDR_DRAMRST# <7>
43 DQ17 DQ21 44 Short Pad
DDR_A_DQS#4 45 VSS VSS 46 2
DQS2#
DM2
DDR_A_DQS4 47 48 Jason 6/24
49 DQS2 VSS 50 DDR_A_D39
DDR_A_D38 51 VSS DQ22 52 DDR_A_D33
1 1 1 1 1 1 1 1 53 DQ18 DQ23 54
DDR_A_D34
55 DQ19 VSS 56 DDR_A_D40 CAD NOTE
DDR_A_D44 57 VSS DQ28 58 DDR_A_D41
CD4
CD8
CD7
CD2
CD3
CD9
2 2 2 2 2 2 2 2 DQ24 DQ29 PLACE THE CAP NEAR TO DIMM RESET PIN
DDR_A_D45 59 60
CD11
CD10
61 DQ25 VSS 62 DDR_A_DQS#5
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
63 VSS DQS3# 64 DDR_A_DQS5
65 DM3 DQS3 66
VSS
DDR_A_D42 67 VSS DQ30 68 DDR_A_D47 +1.35V_MEM
DQ26
DDR_A_D46 69 70 DDR_A_D43
71 DQ27 DQ31 72
VSS VSS 1
+1.35V_MEM DDR_A_CKE0 73 74 DDR_A_CKE1 RD4
<7> DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 <7> 1.8K_0402_1%
C 75 VDD VDD 76 +DDR_VREF_A_DQ0 +DDR_VREF_A_DQ C
77 78 DDR_A_MA15
DDR_A_BS2 79 NC A15 80 DDR_A_MA14 2
<7> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11 1 2
A11
A12/BC#
DDR_A_MA9 85 86 DDR_A_MA7 RD5 2_0402_1%
1 @ @ 87 A9 A7 88
@
1 10U_0603_6.3V6M 1 10U_0603_6.3V6M 1 10U_0603_6.3V6M 1 10U_0603_6.3V6M 1 10U_0603_6.3V6M 1 10U_0603_6.3V6M 1 10U_0603_6.3V6M 1 10U_0603_6.3V6M + 330U_D3_2.5VY_R6M DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
@
@
DDR_A_MA5 91 A8 A5 A6 A4 92 DDR_A_MA4 1 1
CD18
CD17
CD20
CD19
CD16
CD13
CD12
CD15
CD14
2 2 2 2 2 2 2 2 2 93 VDD VDD 94 1.8K_0402_1% 2 RD6 0.022U_0402_16V7K CD21
DDR_A_MA3 95 A3 A2 96 DDR_A_MA2
DDR_A_MA1 97 98 DDR_A_MA0 2
99 A1 A0 100
<7> DDR_A_CLK0 DDR_A_CLK0 101 VDD VDD 102 DDR_A_CLK1 DDR_A_CLK1 <7> 1
CK0
CK1
103
DDR_A_CLK#0
DDR_A_CLK#1
104
<7> DDR_A_CLK#0 CK0# CK1# DDR_A_CLK#1 <7>
105 106 RD7
DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1 DDR_A_BS1 <7> 24.9_0402_1%
BA1
<7> DDR_A_BS0 DDR_A_BS0 109 A10/AP RAS# 110 DDR_A_RAS# DDR_A_RAS# <7>
BA0
111 112
DDR_A_WE# 113 VDD VDD 114 DDR_A_CS#0 2
<7> DDR_A_WE# WE# S0# DDR_A_CS#0 <7>
<7> DDR_A_CAS# DDR_A_CAS# 115 CAS# ODT0 116 DDR_A_ODT0 <7>
117 118
VDD
Layout Note: DDR_A_MA13 119 VDD ODT1 120 DDR_A_ODT1 <7>
A13
DDR_A_CS#1
121
122
NC
Place near <7> DDR_A_CS#1 123 S1# VDD 124 +DDR_VREF_A_CA
VDD
JDIMM1.203,204 125 TEST VREF_CA 126
128
127
VSS
DDR_A_D30 129 VSS DQ36 130 DDR_A_D31
DQ32
DDR_A_D26 131 DQ33 DQ37 132 DDR_A_D25 1 @
133 134
DDR_A_DQS#3 135 VSS VSS 136 2.2U_0402_6.3V6M CD23
DM4
DQS4#
DDR_A_DQS3 137 138 2
139 DQS4 VSS 140 DDR_A_D28
DDR_A_D27 141 VSS DQ38 142 DDR_A_D24
DQ34
DQ39
DDR_A_D29 143 144
VSS
B +0.675V_DDR_VTT 145 DQ35 DQ44 146 DDR_A_D20 DDR3L SODIMM ODT GENERATION B
VSS
DDR_A_D21 147 DQ40 DQ45 148 DDR_A_D16
DDR_A_D17 149 150
151 DQ41 VSS 152 DDR_A_DQS#2 9/17 delete ODT Genertation, connect directly to CPU
153 VSS DQS5# 154 DDR_A_DQS2 refer 546765_2014WW37_SkylakeU_Y_MOW_Rev_1_0
1 1 1 1 1 1 155 DM5 DQS5 156
VSS
VSS
DDR_A_D19 157 158 DDR_A_D18
DDR_A_D22 159 DQ42 DQ46 160 DDR_A_D23
@
161 DQ43 DQ47 162
CD25
CD26
CD27
CD24
2 2 2 2 2 2 DDR_A_D48 163 VSS VSS 164 DDR_A_D53
CD29
CD28
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D52
167 DQ49 DQ53 168
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_A_DQS#6 169 VSS VSS 170
DQS6#
DM6
DDR_A_DQS6 171 DQS6 VSS 172
173 174 DDR_A_D54
DDR_A_D50 175 VSS DQ54 176 DDR_A_D55
DQ50
DQ55
DDR_A_D51 177 DQ51 VSS 178
179 180 DDR_A_D61
DDR_A_D56 181 VSS DQ60 182 DDR_A_D60
DQ61
DQ56
DDR_A_D57 183 DQ57 VSS 184
185 186 DDR_A_DQS#7
187 VSS DQS7# 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D63 191 VSS VSS 192 DDR_A_D58
Short Pad DDR_A_D62 193 DQ58 DQ62 194 DDR_A_D59
195 DQ59 DQ63 196
1 @ 2 197 VSS VSS 198
RD15 0_0402_5% +3VS 199 SA0 EVENT# 200 PCH_SMBDAT <8,21,34>
1 @ 2 201 VDDSPD SDA 202
RD16 0_0402_5% +0.675V_DDR_VTT 203 SA1 SCL 204 +0.675V_DDR_VTT PCH_SMBCLK <8,21,34>
Short Pad VTT VTT
205 206
1 207 GND1 GND2 208
1 @ BOSS1 BOSS2
A 2.2U_0402_6.3V6M CD31 0.1U_0402_10V7K CD32 FOX AS0A621-J4RB-7H A
2 2
CONN@
DELL CONFIDENTIAL/PROPRIETARY
Com
Compal Electronics, Inc.pal Electronics, Inc.pal Electronics, Inc.
Com
Ti Ti Titletletle
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
DDR3
DDR3
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDR3LLL
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Sizezeze Document Numbercument Numbercument Number Revvv
Si Si
Re
Re
Do
Do
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1. 1. 1.0(A00)0(A00)0(A00)
LA
LA
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P-D071P-D071P
Da
Da Date:te:te: T T Thursday, July 09, 2015hursday, July 09, 2015hursday, July 09, 2015 Sh Sh Sheeteeteet 20 20 20 of of of 64 64 64
5 4 3 2 1