Page 720 - Mechatronics with Experiments

706 MECHATRONICS
logic, from the beginning to the end, is scanned every scan period of the PLC. Depending on
the computational power of a PLC, typical scan times are in the order of a few milliseconds
or less per thousand lines of ladder logic code. The benchmark speed of scan time for
per thousand ladder logic code is generally limited to basic logic functions such as AND,
OR, NOT, flip-flop. Special functions, and trigonometric functions, PID control algorithms
implemented in the ladder logic, take a longer computation time. As a result, the scan time
will be slower for ladder logic programs that include many special functions. Therefore,
the scan time estimates given for a PLC by its manufacturer should be interpreted with
this in mind. The actual scan time of a ladder program for an application can be exactly
measured by the software development tools of the PLC. The software development tools
installed and run on a PC for offline program development and debugging purposes also
include utilities that measure the scan time while the program is executing on the PLC. In
the ladder logic programming, sections of the program can be conditional like the if-else
blocks, and subroutines may be called or skipped based on the coded conditions. All of the
PLC ladder logic program is scanned for execution every scan time. It is useful to imagine
the PLC ladder logic as a circular instruction sequence where the CPU goes through the
circle once every scan time period (Figure 9.7).
From a programming point of view, once the racks and slots of a PLC are populated
with I/O interface modules, all of the I/O is memory mapped. There is a one-to-one
memory map between the I/O points on the PLC hardware and the CPU memory addresses
(Figure 9.8). The logic is implemented between the I/O (memory locations) using the logic
functions provided by the ladder logic program. The ladder logic programming focuses on

CPU module Input Output
module: 110 VAC module: 24 VDC
I/O bus
I/O processor &
I/O status memory

Input Output
User memory Terminals Terminals
status status
1 OFF 1
1 OFF 1
2 ON 2 2 2
1001 1002
0001 3
3 3 3
4 4
4 4
0001
Return Return
CPU and memory

Stop 1002
110 V AC
HTR
1001
0001
Start
FIGURE 9.8: The PLC I/O interface, communication bus, CPU, and memory relationship.