Page 36 - NEW Armstrong Book - 2

resistance becomes negligible with respect to the drift component. However, if the MOSFET interface state density in these devices is high, their practical use will be determined mainly by FN tunneling.
Furthermore, charging and discharging the oxide traps lead to a threshold voltage instability wherein an oxygen vacancy has been hypothesized as the origin of the primary oxide traps. Recent advances in technology have removed such instability.
Today, threading dislocations (TDs) are no longer considered killer defects in state-of-the-art wafers. For example, sig- nificant leakage spots show up at TDs in SiC Schottky barrier diodes (SBDs) only when a surface pit is formed at the loca- tion where dislocation intersects the surface of the epitaxial layer; after removing such pits, the SBD exhibits an ideal characteristic despite the TDs.
BPDs and TEDs share the same basic nature; they simply differ depending on the dislocation direction. In fact, inside the boule crystals, conversion from BPD to TED and from TED to BPD is often observed.
During epilayer growth, the threading dislocations in the substrate tend to “migrate” into the epilayer. Some thread- ing screw dislocations convert to Frank-type stacking faults and others to stacking fault complexes, such as carrot and triangular defects. A Frank stacking fault is a partial disloca- tion whose Burgers vector is not parallel to the fault plane so that it can only diffuse and not glide under the action of an applied stress, in contrast to a Shockley partial disloca- tion. Fortunately, one does not have to worry about these threading dislocations in the epilayers, as they are harmless in most power electronic devices. Stacking faults, however, are a major concern, as they impair device performance and reliability, even though the corresponding densities are sig- nificantly smaller (0.2–1 cm–2).
A stacking fault is an interruption of the normal stacking sequence of atomic planes in a closely packed crystal struc- ture. Stacking faults are common defects because of the low stacking-fault energy (14 mJ m–2 for 4H-SiC and 2.9 mJ m–2 for 6H-SiC) and the occurrence of many polytypes in SiC.
For example, in face-centered cubic structures, the normal stacking sequence is ABCABC, etc., but if a stacking fault is introduced, an irregular sequence such as ABCBCABC is generated into the normal stacking order. These irregu- larities carry a certain energy, which is called stacking-fault energy and is measured in energy per unit area.
Typical stacking faults are 3C- or 6H-like laminar regions in 4H-SiC boules. The generation of double Shockley stacking faults in heavily nitrogen-doped SiC has also been reported. Inclusions of foreign polytypes and stacking faults have been greatly reduced by recent progress in polytype control. The typical stacking-fault density along the c-axis is well below 1 cm–1. The generation of stacking faults during SiC epitaxial growth is one of the remaining issues.
One of the most successful techniques to reduce extended defects in SiC boules is the so-called repeated a-face growth (RAF) method. The main concept is the preparation of an almost-dislocation–free seed and subsequent sublima- tion growth on the high-quality seed under stabilized con- ditions. This means that the boule is sliced parallel to the growth direction; because most dislocations are propagating along the growth direction, only a limited number of disloca- tions (mainly BPDs) appear on the surface of the resulting SiC(1120).1 By repeating the process, the density of elemen- tary screw dislocations and TEDs can be lowered. Once this RAF process is done successfully, high-quality SiC{0001} seed crystals can be directly obtained by slicing the high- quality boule, eliminating the need to repeat these compli- cated processes.
Epitaxial growth and doping of SiC
In general, epitaxial growth (or epitaxy) refers to the growth of thin, solid layers on a surface from a chemical reaction with well-controlled quality and thicknesses. The template used for the epitaxial growth of semiconductor materials consists of a substrate, and both homo-epitaxy (substrate and epilayer are of same material) and hetero-epitaxy (sub- strate and epilayer are of different materials) are currently used in the crystal growth technology.
Unlike other semiconductors, SiC has no liquid phase, so the only method to realize SiC wafers implies the use of gas- eous phases. To this end, chemical vapor deposition (CVD) is the standard technique. In CVD, a layer is deposited on a solid monocrystalline surface starting from a gaseous com- ponent, which decomposes on the surface of the substrate. A proper epitaxy should yield precise thickness of the crystal layers, with the right doping level and homogeneity. During CVD, monosilane (SiH4) and propane (C3H8) or ethylene (C2H4)
1 Crystallographic axes are usefully defined using Bravais-Miller indi- ces, a symbolic vector representation consisting of a group of four numbers in a hexagonal system that indicates the orientation of a plane or set of parallel planes of atoms in a crystal. The reciprocals of these intercepts are computed and normalized to give the four indices (a1a2a3c). The notation [a1a2a3c] designates a vector (the direc- tion of the planes), while {a1a2a3c} identifies the set of all planes (or faces) that are equivalent to (a1a2a3c) by the symmetry of the lattice.
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ASPENCORE GUIDE TO SILICON CARBIDE