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Fabricating SiC Devices:
Making the Transition
from Silicon
By Victor Veliadis
developed. Metal evaporation and lift-off can be used as well as sputter metal deposition with dry etching.
• Ohmic contact formation. The high value of SiC/metal bar- rier results in rectifying contacts. Post-metal–deposition anneal is required for ohmic contacts. Anneal temperature, ramp rate, duration, and gas flow must be optimized to maintain surface quality.
• Gate oxides. Poor SiC/SiO2 interface quality reduces MOS inversion layer mobility. Passivation techniques must be developed to improve SiC/SiO2 interface quality.
•Wafer transparency. Transparent wafers complicate CD SEM measurements when the focal plane is determined with the use of an optical microscope. Other metrology tools need software/gain/hardware adjustments to move to wavelengths where SiC is opaque.
• Wafer planarity. Relative lack of planarity in SiC wafers can complicate photolithography and other processing, partic- ularly of high-voltage devices (thick drift epitaxial layers). High-temperature processes can further negatively affect wafer flatness.
•Insulation dielectrics. Thick dielectrics are deposited in SiC, as thick thermally grown oxides are not feasible. Deposited dielectrics are prone to defect incorporation, and the impact on edge termination and device reliability must be assessed.
In the sections that follow, we provide details of SiC etch, doping, and ohmic contact formation. Although SiC MOSFETs and junction barrier Schottky diodes are primarily used in power electronics, the fabrication processes described are applicable to all SiC devices, including JFETs, BJTs, thyris- tors, IGBTs, and PIN diodes, all of which have been success- fully demonstrated in SiC. Inductive coupled plasma (ICP) etch is used to create through-substrate vias in SiC and to
F
or mass silicon carbide commercialization, high- yielding fabrication processes are required. Numerous well-established processes from sili-
con technology have been successfully transferred to SiC.
However, SiC material properties necessitate development of specific processes, the parameters of which must be opti- mized and qualified.1
The following overview of SiC device processing, supple- mented with scanning-electron-microscopy (SEM) images, will focus on the processes that do not carry over from the mature silicon manufacturing world and are thus tailored to SiC. These include:
• Etch. Because of its hardness, SiC is inert against chemical solvents, and only dry etching is practical. Masking materi- als, mask etch selectivity, gas mixtures, control of sidewall slope, etch rates, and sidewall roughness must be devel- oped.
• Substrate thinning. This process is performed to lower the resistance of low-voltage devices (≤1.7 kV) as well as to facilitate handling of the thick epitaxial wafers used in high- voltage device fabrication. SiC material hardness requires special recipes.
• Doping. Conventional thermal diffusion is not practical in SiC because of its high melting point and the low diffusion constant of dopants within SiC. Implantation is commonly used, and the species, dose, energy, temperature, and masking materials must be optimized. Post-implantation SiC recrystallization and implant-activation anneal method (furnace, rapid thermal annealing, etc.), temperature, ramp rate, duration, and gas flow need to be developed. Anneal- protective cap layers to minimize SiC wafer surface degra- dation need to be deposited.
•Metallization. CTE-matched metals must be evaluated, suitable resist type selected, and undercut lift-off profiles
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ASPENCORE GUIDE TO SILICON CARBIDE