Page 98 - Programmable Logic Controllers, Fifth Edition - Mobile version

single scan can vary from about 1 to 20 ms. If a controller
input image table will be set to a 1.
has to react to an input signal that changes states twice dur- electrical continuity), the corresponding bit in the
ing the scan time, it is possible that the PLC will never be In a rung of any hardwired circuit there must be electrical
able to detect this change. For example, if it takes 8 ms for continuity in order for the load to energize. The rung has
the CPU to scan a program, and an input contact is opening electrical continuity only when the current flow is estab-
and closing every 4 ms, the program may not respond to the lished in a path from one side of the power rail to the other.
contact changing state. The CPU will detect a change if it There is no electrical continuity in the PLC ladder logic
occurs during the update of the input image table file, but program. Instead, the rung must be evaluated in terms of
the CPU will not respond to every change. The scan time is logical continuity rather than electrical continuity. When
a function of the following: there is a continuous path of true conditional instructions
• The speed of the processor module in a rung, logical continuity exists; accordingly the output
• The length of the ladder program instruction is true and the status bit will be set to a 1 (ON).
• The type of instructions executed The controller evaluates ladder logic rung instructions
• The actual ladder true/false conditions based on the rung condition preceding the instruction
(rung-condition-in), as illustrated in Figure 5-10.
The actual scan time is calculated and stored in the
PLC’s memory. The PLC computes the scan time each • If the rung-condition-in to an input instruction is
time the END instruction is executed. Scan time data can true, the controller evaluates the instruction and sets
be monitored via the PLC programming. Typical scan the rung-condition-out to match the results of the
time data include the maximum scan time and the last evaluation.
scan time. • If the instruction evaluates to true, the rung-
The scan is normally a continuous and sequential pro- condition-out is true.
cess of reading the status of inputs, evaluating the control • If the instruction evaluates to false, the rung-
logic, and updating the outputs. Figure 5-9 shows an over- condition-out is false.
view of the data flow during the scan process. For each • If the rung-condition-in to an output instruction is
rung executed, the PLC processor will: true, the rung-condition-out is set to true.

• Examine the status of the input image table bits. • If the rung-condition-in to an output instruction is
• Solve the ladder logic in order to determine logical false, the rung-condition-out is set to false.
continuity. Figure 5-11 illustrates the scan process applied to a
• Update the appropriate output image table bits, if simple single rung program. The operation of the scan
necessary. process can be summarized as follows:
• Copy the output image table status to all of the output • If the input device connected to address I:3/6 is
terminals. Power is applied to the output device if the closed, the input module circuitry senses voltage at
output image table bit has been previously set to a 1. the input terminal and a 1 (ON) condition is entered
• Copy the status of all of the input terminals to the into the input image table bit I:3/6.
input image table. If an input is active (i.e., there is • During the program scan, the processor examines
bit I:3/6 for a 1 (ON) condition.
Input Input Output Output
data • In this case, because input I:3/6 is 1, the rung is said
Input image image data Output
modules table table modules to be TRUE or have logic continuity.
file file
Input Output
Examine Return instructions instructions
data result
L1 S1 PL1 L2
Program S1 PL1
Rung-in Rung-out
condition condition
Check/compare/examine
specific conditions Take some action S2 PL2
S2 PL2
Figure 5-9 Overview of the data flow during the scan
process. Figure 5-10 Evaluating ladder logic rung conditions.

Basics of PLC Programming Chapter 5 79

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