Page 9 - Multipath MIPS

Multi-issue Architectures (CPI<1)

 Issue more than one instruction per cycle. Two classes:
 Static/Dynamic Scheduled Superscalar
 Very Long Instruction Word (VLIW)
 Static superscalar and the VLIW processor rely on the
compiler for scheduling the program instructions (unrolling)
 Dynamic superscalar adds issue and commit logic to
support multiple issue/commit of instructions per clock cycle

 Superscalars require further aggressive fetching &
prediction/speculation techniques to feed the processor
 BTC/Branch Folding/Return Address Predictor(IJ)
 Integrated Fetch Unit (Auto. Pre-fetch/fetch across C. blocks)
 Memory dependency prediction/Value prediction

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