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NPP CPU Architecture, Addressing Modes and Data Transfer Schemes 399
Condition ZF CF SF
(r ) = (r ) 1 0 0
1
2
(r ) > (r ) 0 0 0
2
1
(r ) < (r ) 0 1 1
2
1
CF (Carry Flag) indicates whether a bor- CF (Ho$ar âcoJ) g§Ho$V H$aVo h¢ {H$ Š`m AÝV _| EH$
row is needed at the end or not.
~m°amo H$s Amdí`H$Vm h¡ `m Zht&
CMP r, m
CMP m, r
CMP r, data
CMP m, data
Same as CMP r , r only difference is in CMP r , r Ho$ g‘mZ hr Am°naoÝS> ‘| Ho$db AÝVa
1
2
1
2
operands. NPP hmoVm h¡&
5.4.3 Program Control Instructions 5.4.3 àmoJ«m‘ H§$Q´>mob BÝñQ´>³eÝg
Branching Instructions ~«m§qMJ BÝñQ´>³eÝg
Loop Instructions byn BÝñQ´>³eÝg
Interrupt Instructions BÝQ>aßQ> BÝñQ´>³eÝg
Branching Instructions ~«m§qMJ BÝñQ´>ŠeÝg
The instructions which break the normal BÝñQ´>ŠeÝg Omo àmoJ«m_ EŠOrŠ`yeZ Ho$ gm_mÝ` {gŠd|g
sequence of program execution are called H$mo Vmo‹S>Vo h¢ ~«m§qMJ BÝñQ´>ŠeÝg H$hcmVo h¢& 8086 ‘|
Branching Instructions. There are two types of
branching instructions in 8086: ~«m§qMJ BÝñQ´>ŠeÝg Ho$ Xmo àH$ma hmoVo h¢:
Intrasegment · BÝQ´>mgoJ_oÝQ>
Intersegment · BÝQ>agoJ_oÝQ>
Intrasegment: This type of branch gives BÝQ´>mgoJ_oÝQ>: Bg àH$ma H$s ~«mÝM Cgr goJ_oÝQ> Ho$
rise to a transfer of control within the same AÝXa H$ÊQ´>moc Q´>mÝg\$a H$aZo XoVr h¡& H$moS> goJ_oÝQ> (CS)
segment. Code segment (CS) Register remain a{OñQ>a An[ad{V©V ahVm h¡& Ho$dc IP _moS>r\$m` hmoVm h¡&
unchanged. Only IP is modified. If 8-bit dis-
placement is added it is called short and if 16- `{X 8 {~Q> {S>gßcog_oÝQ> Omo‹S>m OmVm h¡ Omo Bgo em°Q>© H$hm
bit displacement is added to IP it is called NEAR. OmVm h¡ VWm `{X 16 {~Q> {S>gßcog_oÝQ> Omo‹S> OmVm h¡ Vmo
The operand may refer to 8-bit or 16-bit num- Bgo NEAR H$hm OmVm h¡& Am°naoÝS> 8 {~Q> `m 16 {~Q>
ber. It can further be divided to direct and In- g§»`m H$m gÝX^© {X`m Om gH$Vm h¡& Bgo AmJo S>m`aoŠQ>
direct mode. In a direct mode the displacement VWm BZS>m`aoŠQ> _moS> _| {d^m{OV {H$`m Om gH$Vm h¡&
is directly specified. In indirect mode a register S>m`aoŠQ> _moS> _| {S>gßcog_oÝQ> H$mo grYo hr {ZYm©[aV {H$`m