Page 403 - FUNDAMENTALS OF COMPUTER

NPP

NPP CPU Architecture, Addressing Modes and Data Transfer Schemes 403

JMP r : Jump to an address specified by JMP r : Am°\$goQ> Ûmam {ZYm©[aV EH$ ES´>og na Oån
16
16
the offset which is in the 16-bit register. Con- H$aVm h¡ Omo 16 {~Q> a{OñQ>a _| h¡& r Ho$ H$ÝQ>oÝQ²>g IP _|
16
tents of r are transferred into IP. Code seg- Q´>mÝg\$a {H$`o OmVo h¢& H$moS> goJ_oÝQ> a{OñQ>a An[ad{V©V
16
ment register CS remains unchanged. There- ahVm h¡& Bg{cE `h EH$ BÝQ´>mgoJ_oÝQ> ~«mÝM BÝñQ´>ŠeZ h¡&
fore it is an Intrasegment branch instruction.
e.g. JMP AX , will be executed as follows: JMP AX , {ZåZ àH$ma EŠOrŠ`yQ> hmoJm:
(IP) (AX)
JMP m : Unconditional Jump to a loca- JMP m : _o_moar dS>© Ûmam {ZYm©[aV EH$ cmoHo$eZ na
16
16
tion specified by memory word. Two bytes AZH$ÊS>reZc Oån H$aVm h¡& DS _| _o_moar go Xmo ~mBQ> IP
from memory in DS are transferred to IP.
_| Q´>mÝg\$a H$s OmVr h¢&
e.g. JMP [SI]
Two bytes from [SI] and [SI + 1] in data S>mQ>m goJ_oÝQ> _| [SI] VWm [SI + 1] go Xmo ~mBQ²>g IP
segment are transferred to IP. CS remains un- _| Q´>mÝg\$a H$s OmVr h¢& CS An[ad{V©V ahVm h¡& Bg{cE
changed. Therefore it is intrasegment branch `h BÝQ´>mgoJ_oÝQ> ~«mÝM BÝñQ´>ŠeZ h¡&
instruction.
JMP m : m is a memory which points to JMP m : m EH$ _o_moar h¡ Omo EH$ 32 {~Q> g§»`m
32
32
32
32
a 32-bit number (4 bytes). Low order 16-bits (4 ~mBQ>) H$mo B§{JV H$aVr h¡& cmo Am°S>©a 16 {~Q²>g IP _|
are loaded into IP and High order 16-bits are VWm hmB Am°S>©a 16 {~Q²>g CS _| cmoS> H$s OmVr h¢& My±{H$
loaded into CS. Since CS and IP both are modi- CS VWm IP XmoZm| _| n[adV©Z hmoVm h¡ Bg{cE Bgo BÝQ>agoJ_oÝQ>
fied, it is called Intersegment branch instruc- ~«mÝM BÝñQ´>ŠeZ H$hVo h¢& Agoå~ca S>mBao{ŠQ>d g§Ho$V
tion. Assembler directive must be used to indi-
cate that DWORD is a double word memory H$aZo Ho$ {cE Cn`moJ {H$`m OmZm Amdí`H$ h¡ {H$ DWORD
pointer. EH$ S>~c dS>© _o_moar nm°BÝQ>a h¡&
e.g. JMP DWORD PTR [BX]
BX points to four locations from where IP BX Mma cmoHo$eÝg H$mo B§{JV H$aVm h¡ Ohm± go IP VWm
and CS will be loaded as follows: CS {ZåZ àH$ma cmoS> {H$`o Om`|Jo:

[BX]
[BX + 1] (IP)

[BX + 2] (CS)
[BX + 3]
Conditional Jump Instructions: The H$ÊS>reZc Oån BÝñQ´>ŠeÝg: àmoJ«m_ H$ÝQ´>moc {ZYm©[aV
program control jumps to the specified location cmoHo$eZ na V^r Oån H$aVm h¡ O~ {ZpíMV H$ÊS>reZ
only when certain conditions are satisfied.
These instructions are used with status flags g§VwîQ> hmoVr h¡& `o BÝñQ´>ŠeÝg ñQ>oQ>g âco½g VWm CMP
and CMP instruction. First processor checks BÝñQ´>ŠeZ Ho$ gmW Cn`moJ H$s OmVr h¢& nhco àmogoga
the value of flag bit in the flag register. âcoJ a{OñQ>a _| âcoJ {~Q> H$s d¡ë`y H$s Om±M H$aVm h¡&
Conditional Jump Instruction Related to ñQ>oQ>g âcoJ {~Q²>g go gå~pÝYV H$ÊS>reZc Oån
Status Flag bits: The flag bits, OF, CF, SF, PF and BÝñQ´>ŠeZ: âcoJ {~Q²>g, OF, CF, SF, PF VWm ZF H$mo