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NPP CPU Architecture, Addressing Modes and Data Transfer Schemes 405

conditional flags. The flags are set or reset {ZYm©[aV cmoHo$eZ na Oån H$aoJm& âco½g H$mo goQ> `m [agoQ>
because of relative magnitudes of operands in {H$`m OmVm h¡ Š`m|{H$ CMP BÝñQ´>ŠeZ _| Am°naoÝS²>g H$m
CMP instruction. These branch instructions are
different for signed and unsigned comparison: [aco{Q>d _¡{½ZQ²>`yS> hmoVm h¡& `o ~«mÝM BÝñQ´>ŠeÝg gmBÝS>
VWm AZgmBÝS> VwcZm Ho$ {cE {^ÝZ h¢:
Unsigned Comparison: AZgmBÝS> VwbZm…
CMP opr1, opr2
JE d 8 Jump if equal; opr1=opr2

JA d 8 Jump if above; opr1>opr2
or JNBE d 8 Jump if not below or equal
JB d 8 Jump if below; opr1<opr2
or JNAE d 8 Jump if not above or equal
JAE d 8 Jump if Above or equal opr2>opr2
or NPP Jump if not below
JNB d
8
JBE d 8 Jump if below or equal
or JNA d 8 Jump if not above
Signed Comparison: gmBÝS> VwbZm…
JE d 8 Jump if equal; opr1=opr2
JG d 8 Jump if greater; opr1>opr2

or JNLE d 8 Jump if not less or equal
JGE d 8 Jump if greater or equal
or JNL d\8 Jump if not less (opr1>opr2)
JL d 8 Jump if less; opr1<opr2
or JNGE d 8 Jump if not greater or equal
or JLE d 8 Jump if less or equal; opr1<opr2
or JNG d 8 Jump if not greater

LOOP instructions cyn BÝñQ´>ŠeÝg
These instructions are just combination of `o BÝñQ´>ŠeÝg Ho$dc Xmo BÝñQ´>ŠeÝg DEC VWm JNZ
two instructions; DEC and JNZ but they donot H$m g§`moJ h¢ {H$ÝVw do âco½g H$mo à^m{dV Zht H$aVo h¢&
affect flags.
LOOP d : First decrement CX by 1. Then LOOP d : nhco CX H$mo 1 KQ>mVm h¡& BgHo$ níMmV²
8
8
jump to the 8-bit signed displacement if 8 {~Q> gmBÝS> {S>gßcog_oÝQ> na Oån H$aVm h¡& `{X
(CX) ≠ 0. Thus it can be consider as a (CX) ≠ 0. Bg àH$ma, Bgo {ZåZ Xmo BÝñQ´>ŠeÝg Ho$ g§`moJ
combination of following two instructions:
Ho$ ê$n _| {dMma {H$`m Om gH$Vm h¡: