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NPP         CPU Architecture, Addressing Modes and Data Transfer Schemes         407


                  3.  CS is pushed on stack.                  3.  CS ñQ>¡H$ na ^oOm OmVm h¡ &
                  4.  CS is loaded from (4n  + 2) and (4n  + 3)  4.  CS H$mo (4n + 2) VWm (4n + 3) {\${OH$c cmoHo$eÝg
                      physical locations.                         H$mo cmoS> {H$`m OmVm h¡&
                  5.  IP is pushed on stack.                  5.  IP ñQ>¡H$ na ^oOm OmVm h¡&
                  6.  IP is loaded from (4n) and (4n + 1) physical  6.  IP H$mo (4n) VWm (4n + 1) {\${OH$c ES´>ogog go cmoS>
                      addresses.                                  {H$`m OmVm h¡&
                      Next instruction address is calculated from  AJcm BÝñQ´>ŠeZ ES´>og IP VWm CS H$s Z`r d¡ë`y go
                  new values of IP and CS. This is how the pro-  JUZm {H$`m OmVm h¡& Bg H$maU àmoJ«m_ H$ÊQ´>moc Z`o g~éQ>rZ
                  gram control jumps to a new subroutine. The  na Oån H$aVm h¡& Bg g~éQ>rZ H$m àmapå^H$ ES´>og BÝQ>aßQ>
                  beginning address of this subroutine is called
                  interrupt vector address and the subroutine is  doŠQ>a ES´>og H$hcmVm h¡ VWm g~éQ>rZ H$mo BÝQ>aßQ> g{d©g
                  called Interrupt service Routine (ISR).     éQ>rZ (ISR) H$hm OmVm h¡&
                      IRET: Interrupt Return; used at the end of  IRET:  BÝQ>aßQ> [aQ>Z© H$mo H$m°qcJ àmoJ«m_ go dmng
                  ISR to return to the calling program.       AmZo Ho$ {cE ISR Ho$ AÝVa _| Cn`moJ {H$`m OmVm h¡&
                      Following  sequence of operations take      Am°naoeÝg H$m {ZåZ{c{IV {gŠd|g ahVm h¡:
                  place:              NPP
                  1.  Two bytes of stack are transferred to IP.  1. ñQ>¡H$ H$s Xmo ~mBQ²>g IP _| Q´>mÝg\$a H$s OmVr h¢&
                  2.  Next to bytes are poped into CS.        2. AmJo H$s ~mBQ> CS _| nm°ßS> H$s OmVr h¢&
                  3.  Next two bytes are poped into flag register.  3. AmJo H$s Xmo ~mBQ²>g âcoJ a{OñQ>a _| nm°ßS> H$s OmVr h¢&
                      The  values  of  CS and  IP points of  the  CS VWm IP H$s d¡ë`yO BÝñQ´>ŠeZ Ho$ BÝñQ´>ŠeZ h¢
                  instruction which follows INTn instruction in  Omo H$m°qcJ àmoJ«m_ _| INTn BÝñQ´>ŠeZ H$m nmcZ H$aVo h¢&
                  the calling program. Program control returns
                  to this next location.                      àmoJ«m_ H$ÊQ´>moc Bg AJcr cmoHo$eZ H$mo [aQ>Z© H$aVm h¡&
                      INTO: Interrupt on Overflow, INT4 is ex-    INTO: BÝQ>aßQ> Am°Z Amodaâcmo, INT4 EŠOrŠ`yQ>
                  ecuted whenever OF is set.                  hmoVm h¡ O~ H$^r OF goQ> hmoVm h¡&

                   5.4.4 Machine  Control  Instructions       5.4.4 _erZ H$ÊQ´>moc BÝñQ´>ŠeÝg

                  STC:   Set Carry; used to set CF thus CF = 1 is  STC:  goQ> Ho$ar H$mo CF goQ> H$aZo Ho$ {cE Cn`moJ {H$`m
                         obtained.                                   OmVm h¡& Bg àH$ma CF = 1 àmßV hmoVm h¡&
                  CMC:   Complement carry; the value of CF is  CMC: H$m°påßc_oÝQ> Ho$ar; CF H$s d¡ë`y H$m°påßc_oÝQ> H$s
                         complemented.                               OmVr h¡&

                  STD:   Set direction  flag; thus DF =  1 is  ob-  STD: goQ> S>mBaoŠeZ âcoJ; Bg àH$ma DF = 1 àmßV
                         tained.                                     hmoVm h¡&

                  STI :  Set Interrupt  flag, Thus  IF =  1 is  ob-  STI :  goQ> BÝQ>aßQ> âcoJ, Bg àH$ma IF = 1 àmßV hmoVm
                         tained                                      h¡&

                  CLC:   Clear carry flag, CF = 0 is obtained  CLC:  Šcr`a Ho$ar âcoJ, CF = 0 àmßV hmoVm h¡&
                  CLI:   Clear Interrupt flag, Thus IF = 0 is ob-  CLI:  Šcr`a BÝQ>aßQ> âcoJ, IF = 0 àmßV hmoVm h¡&
                         tained.
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