Page 411 - FUNDAMENTALS OF COMPUTER

NPP

NPP CPU Architecture, Addressing Modes and Data Transfer Schemes 411

method is suitable when small amount of in- ñWmZm§VaU H$aZm h¡Ÿ& VrZ àH$ma go àmoJ«måS> S>mQ>m Q´>m§g\$a
formation is to be transferred. There are three hmoVm h¡…
types of programmed data transfer:
(i) Synchronous Data Transfer (i) [gÝH«$moZg S>mQ>m Q´>m§g\$a
(ii) Asynchronous Data Transfer (ii) E[gÝH«$moZg S>mQ>m Q´>m§g\$a
(iii) Interrupt Controlled Data Transfer (iii)B§Q´>ßQ> H§$Q´>moëS> S>mQ>m Q´>m§g\$a

(i) Synchronous Data Transfer (i) {gÝH«$moZg S>mQ>m Q´>m§g\$a
This type of data transfer is suitable when `o VoO J{V dmbo BZnwQ>-AmCQ>nwQ> Ho$ {bE Cn`wŠV
IO device matches in speed with the CPU. In-
put-output port related instructions are used S>mQ>m Q´>m§g\$a hmoVm h¡ & nmoQ>© go g§~§{YV {ZX}em| H$m
for data transfer. For example, IN and OUT Cn`moJ H$aHo$ S>mQ>m Q´>m§g\$a {H$`m OmVm h¡ & O¡go, IN
instruction can be used. IN instruction accepts VWm OUT B§ñQ´>ŠeZŸ& IN {ZX}e go S>mQ>m àmá {H$`m
data from the specified port. Similarly OUT
instruction sends data to the specified output OmVm h¡ VWm OUT {ZX}e go S>mQ>m CPU Ûmam AmCQ>nwQ>
port. As soon as IN and OUT instructions are H$mo àXmZ {H$`m OmVm h¡Ÿ& S>mQ>m H$m AmXmZ-àXmZ nmoQ>©
executed data is transferred between IO de- go {H$`m OmVm h¡Ÿ&
vices and CPU.
(ii) Asynchronous Data Transfer (ii) E{gÝH«$moZg S>mQ>m Q´>m§g\$a
The data transfer from CPU to IO devices Bg {d{Y H$m Cn`moJ Yr_o BZnwQ>-AmCQ>nwQ> `wpŠV`m|
may be very fast but the reverse cannot be so
fast. Some IO devices are very slow. Their tim- Ho$ {bE {H$`m OmVm h¡Ÿ& Bg {d{Y _| CPU Ûmam EH$ {g¾b
ing characteristics cannot be predicted. Such `w{º$ H$mo {X`m OmVm h¡Ÿ& `wpŠV Yr_r hmoVr h¡, Bg{bE dh
IO devices use asynchronous mode of data VËH$mb S>mQ>m àXmZ Zht H$aVrŸ& Bg{bE CPU bJmVma
transfer. In this type of data transfer CPU ini-
tiates the IO device to transfer data. But since `wpŠV H$s Om§M H$aVo ahVm h¡Ÿ& O¡go `wpŠV V¡`ma hmo OmVr
IO is slow and it may take long time to supply h¡, S>mQ>m Q´>m§g\$a H$a {X`m OmVm h¡ & Bg {d{Y _| CPU
the data, the CPU keeps checking the status of H$m à^mdr Cn`moJ Zht hmo nmVm h¡ Š`m|{H$ Á`mXmVa g_`
IO. The CPU waits for the desired data. When
the device becomes ready, the CPU accetps data CPU BZnwQ>-AmCQ>nwQ> H$s Om§M H$aZo _| bJm ahVm h¡Ÿ&
after issuing instruction. This method gives O¡go Bg àH$ma Ho$ S>mQ>m Q´>m§g\$a H$m Cn`moJ ADC
inefficient utilisation of CPU, because the time (Analog to Digital Converter) _| {H$`m OmVm h¡Ÿ&
of CPU is wasted in checking the status of IO
device. The example of this type of data trans- CPU Ûmam ADC H$mo àma§{^H$ {g½Zc {X`m OmVm h¡Ÿ& BgHo$
fer is Analog to Digital Converter (ADC). The ~mX CPU cJmVma ADC H$mo MoH$ H$aVm h¡Ÿ& O¡go hr ADC
CPU gives start of conversion signal, to initiate H$m H$m`© nyam hmoVm h¡, CPU H$mo EH$ {g½Zc {_cVm h¡
ADC. When conversion is completed ADC gives
end of conversion signal to CPU, Now CPU Am¡a `h S>mQ>m H$mo n‹T> coVm h¡Ÿ&
reads Data.