Page 413 - FUNDAMENTALS OF COMPUTER

NPP

NPP CPU Architecture, Addressing Modes and Data Transfer Schemes 413

without the involvement of CPU. Suppose you DMA go hmo Vmo A{YH$ VoO hmoJmŸ& O¡go; H$moB© ~Zm hþAm
want to take printout of a document, it must be àmoJ«m_ ao_ go grYo-grYo hmS>©{S>ñH$ _| god H$aZmŸ&
directly transferred from RAM to the printer.

DMA Controller DMA H§$Q´>moba
This is a device which handles many IO `h dh `wpŠV h¡, Omo AZoH$ BZnwQ>-AmCQ>nwQ
devices which want to perform DMA opera-
tion. The IO devices make request to the DMA `wpŠV`m| H$mo DMA Am°naoeÝg gånÞ H$aZo H$s gw{dYm
controller for performing DMA operation. The àXmZ H$aVr h¡Ÿ& `o BZnwQ>-AmCQ>nwQ> `w{º$`m± DMA
controller than select one of them depending H§$Q´>moba go DMA Am°naoeÝg gånÞ H$aZo H$m {ZdoXZ
upon the priority scheme. The request is then H$aVr h¢Ÿ& DMA H§$Q´>moba àmW{_H$Vm Ho$ AmYma na {H$gr
sent to the CPU. The DMA request signal is
often referred to as HOLD. This is the request EH$ H$s {ZdoXZ H$mo MwZH$a CPU H$mo XoVm h¡Ÿ& DMA
to the CPU to leave the control of the bus. The {ZdoXZ {g½Zb H$mo HOLD H$hVo h¢Ÿ& O¡go hr CPU H$mo
CPU provides DMA acknowledgement or DMA {ZdoXZ àmá hmoVm h¡, DMA E³Zm°boO‘|Q> ¶m
HOLD Acknowledgement (HLDA) signal to
DMA controller. At the same time CPU leaves HLDA (HOLD Acknowledgement) {g¾b àXmZ
the control of the bus by placing the bus in H$aVm h¡Ÿ& gmW hr ~g H$mo hmB©BpånS>|g ñQ>oQ> _| nhþ±Mm
high impedance state. Now the DMA control- XoVm h¡Ÿ& A~ DMA H§$Q´>moba àmogoga H$m H$m`© H$aVm h¡Ÿ&
ler becomes bus master and it works as a pro- grYo-grYo _o_moar Am¡a IO `wpŠV`m| Ho$ _Ü` S>mQ>m Q´>m§g\$a
cessor. When the complete data is transferred,
the DMA controller again leaves the control of hmoVm h¡Ÿ& O¡go hr g§nyU© S>mQ>m Q´>m§g\$a hmo OmVm h¡ CPU
the bus to the CPU. The diagram depicts the {\$a go ~g H$m ñdm_r hmo OmVm h¡& {ZåZ {MÌ H$mo XoImo…
details:

CPU Printer MT FD HD

DMA
Controller
HOLD

HLDA
System Bus

Memory
RAM ROM