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418 Fundamentals of Computers NPP

Q.16. ADD B instruction belongs to following addressing mode:

ADD B BÝñQ´>³eZ {ZåZ{b{IV ES´>oqgJ ‘moS> ‘| AmVm h¡…
(a) Direct / S>m¶ao³Q> (b) Indirect / BZS>m¶ao³Q>
(c) Register / a{OñQ>a (d) Implied / BåßbmBS>
Q.17. STAX D instruction belongs to following addressing mode:

STAX D BÝñQ´>³eZ {ZåZ{b{IV ES´>oqgJ ‘moS> ‘| AmVm h¡…
(a) Direct / S>m¶ao³Q> (b) Indirect / BZS>m¶ao³Q>
(c) Register / a{OñQ>a (d) Implied / BåßbmBS>
Q.18. In which type of CPU the operation is performed over top two locations of the stack:

CPU Ho$ {H$g àH$ma ‘| Am°naoeZ ñQ>¡H$ Ho$ D$na Ho$ Xmo bmoHo$eZ na gånÝZ {H$¶m OmVm h¡…
(a) Accumulator based CPU / E³¶y‘wboQ>a ~oñS> CPU
(b) General register based CPU / OZab a{OñQ>a ~oñS> CPU
(c) Stack-organised CPU / ñQ>¡H$ Am°J}ZmBÁS> CPU

(d) None of these / BZ‘| go H$moB© Zht
Q.19. CPU is efficiently utilized in .............. data transfer.
CPU H$mo ............. S>mQ>m Q´>mÝg’$a ‘| Hw$ebVmnyd©H$ Cn¶moJ {H$¶m OmVm h¡&
(a) Cycle stealing mode / gm¶H$b ñQ>rqbJ ‘moS> (b) Burst mode / ~ñQ>© ‘moS>

(c) Interrupt-driven / BÝQ>aßQ> {S´>dZ (d) None of these / BZ‘| go H$moB© Zht
Q.20. ADD R , R , R instruction will add:
1
2
3
ADD R , R , R BÝñQ´>³eZ Omo‹S>oJm…
3
2
1
(a) R , R , R 3 (b) R , R 2 (c) R , R 3 (d) R , R 3
1
1
2
2
1
Answer Keys..... 20. (c) 19. (a) 18. (c) 17. (b) 16. (c) 15. (a)
11. (c)
10. (c)
9. (a)
12. (d)
13. (a)
14. (b)
8. (d)
2. (c)
1. (d)
6. (c)
7. (c)
5. (d)
3. (a)
4. (b)
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