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                   416                          Fundamentals of Computers                          NPP


                  Q.18. Explain assembly language  instruction format.
                        Agoå~br b¢½doO BÝñQ´>³eZ ’$m°‘}Q> g‘PmB¶o&
                  Q.19. What do you mean by zero, one, two and three address (operand) instructions ? Explain
                        with suitable examples.
                        Oramo, dZ, Qy> VWm W«r ES´>og (Am°naoÝS>) BÝñQ´>³eÝg go AmnH$m ³¶m Ame¶ h¡? Cn¶w³V CXmhaUm| g{hV
                        g‘PmB¶o&
                  Q.20. Explain different addressing modes giving suitable examples.
                        Cn¶w³V CXmhaU XoH$a {d{^Þ ES´>oqgJ ‘moS²>g g‘PmB¶o&
                  Q.21. What are different ways with which the CPU can be organised ? Explain giving suitable
                        examples.
                        {d{^Þ VarHo$ ³¶m h¢ {OZgo CPU H$mo Am°J}ZmBO {H$¶m Om gH$Vm h¡? CXmhaU XoH$a g‘PmB¶o&
                                        Objective Type Questions


                   Q.1. Which of these is not a CPU architecture:
                        BZ‘| go H$m¡Z EH$ CPU Am{H©$Q>o³Ma Zht h¡…
                        (a) General Register / OZab a{OñQ>a    (b) Accumulator Based / E³¶y‘wboQ>a ~oñS>
                        (c) Stack organized / ñQ>¡H$ Am°J}ZmBÁS>  (d) None of these / BZ‘| go H$moB© Zht
                   Q.2. Which of the following uses zero operand instructions:
                        {ZåZ{b{IV ‘| go H$m¡Z Oramo Am°naoÝS> BÝñQ´>³eÝg H$m Cn¶moJ H$aVm h¡…
                        (a) General Register / OZab a{OñQ>a    (b) Accumulator Based / E³¶y‘wboQ>a ~oñS>
                        (c) Stack organized / ñQ>¡H$ Am°J}ZmBÁS>  (d) None of these / BZ‘| go H$moB© Zht
                   Q.3. Accumulator based CPU uses ................ operand instructions:
                        E³¶y‘wboQ>a ~oñS> CPU ............ Am°naoÝS> BÝñQ´>³eÝg Cn¶moJ H$aVm h¡…
                        (a) 1              (b) 2               (c) 3               (d) 4
                   Q.4. The data transfer instruction:
                        S>mQ>m Q´>mÝg’$a BÝñQ´>³eZ:
                        (a) Changes  the source contents / gmog© H$ÝQ>oÝQ²>g H$mo n[ad{V©V H$aVm h¡
                        (b) The source contents remain unchanged / gmog© H$ÝQ>oÝQ²>g An[ad{V©V ahVm h¡
                        (c) Source becomes empty / gmog© Imbr hmo OmVm h¡
                        (d) The destination contents remain unchanged / S>oñQ>rZoeZ H$ÝQ>oÝQ²>g An[ad{V©V ahVm h¡
                   Q.5. The data is transfer without CPU intervention:
                        S>mQ>m CPU BÝQ>adoÝeZ Ho$ {~Zm Q´>m§g’$a hmoVm h¡…

                        (a) Using Interrupt / BÝQ>aßQ> H$m Cn¶moJ H$aHo$  (b) Synchronous / {gÝH«$moZg
                        (c) Asynchronous / E{gÝH«$moZg         (d) DMA
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