Page 414 - FUNDAMENTALS OF COMPUTER

NPP

414 Fundamentals of Computers NPP

For example, IC 8237/8257 are four chan- CXmhaUV, IC 8237/8257 Mma MoZb DMA H§$Q´>moba
nel DMA Controllers. It means these ICs are h¡& AWm©V² `o Mma Eogr `wpŠV`m| go Omo‹S>o Om gH$Vo h¢ Omo
capable of handling four IO devices which want DMA S>mQ>m Q´>m§g\$a H$aZm MmhVr h¢Ÿ& `o EH$ ~ma _|
to perform DMA data transfer. It can transfer A{YH$V_ 16KB H$m S>mQ>m Q´>m§ñ\$a H$a gH$Vo h¢, BÝh|
16 KB in one cycle and can be used with 8085 _mBH«$moàmogoga 8085, 8086/8088 Am{X Ho$ gmW
and 8086/8088. Cn`moJ {H$`m Om gH$Vm h¡Ÿ&

Modes of DMA Data Transfer DMA S>mQ>m Q´>m§g\$a Ho$ _moS>

There are two ways in which the DMA Xmo àH$ma go DMA g§nÝZ {H$`m Om gH$Vm h¡…
data transfer can be done:
1. Burst Mode of data Transfer. 1. S>mQ>m Q´>mÝg’$a H$m ~ñQ>© _moS> (I§S>m| _| Q´>m§g\$a)
2. Cycle stealing mode of data Transfer. 2. S>mQ>m Q´>mÝg’$a H$m gmBH$b ñQ>rqbJ ‘moS> (gmBH$b
MwamH$a)
1. Burst Mode: In this mode of Data transfer 1. ~ñQ>© _moS>: Bg_| g§nyU© ãbm°H$ H$s OmZH$mar EH$
a block of data is transferred. The CPU remains gmW Q´>m§g\$a hmoVr h¡& nyao g_` CPU {ZpîH«$` hmo OmVm
idle for the whole period of DMA data transfer, h¡ ŸŠ`m|{H$ CPU H$mo ~g H$m {Z`§ÌU V~ VH$ dmng Zht
because the Control of the system bus is trans-
ferred to the CPU only when the complete block {X`m OmVm O~ VH$ {H$ g§nyU© OmZH$mar Q´>m§g\$a Zht hmo
of data is transferred. Thus, this is a faster data JB© hmo& AË`{YH$ J{V go S>mQ>m Q´>m§g\$a hmoVm h¡ Ÿna§Vw
transfer technique but it gives less efficient EH$ hm{Z `h hmoVr h¡ {H$ CPU H$m à^mdr Cn`moJ Zht
utilisation of the CPU. It is used with hard disk hmo nmVm& Bg àH$ma H$m S>mQ>m Q´>m§g\$a âbm°nr d
and floppy disks because the transfer cannot be hmS>©{S>ñH$ Ho$ gmW H$aVo h¢ Š`m|{H$ BZH$mo ~rM _| Zht
stopped in the midway to avoid loss of data. amoH$m Om gH$Vm h¡&

2. Cycle stealing mode: In this mode first 2. gmBH$b ñQ>rqbJ _moS: Bg_| DMA H§$Q´>moba
the status of the CPU is checked by the DMA bJmVma CPU H$s Om§M H$aVo ahVm h¡& {Og g_` CPU
controller. If the CPU is not using system Bus, H$mo ~g H$m H$m`© Zht n‹S>Vm, V~ `h DMA {H«$`m H$a
DMA data transfer is performed. Whenever boVm h¡& bo{H$Z O¡go hr CPU H$mo ~g H$s Amdí`H$Vm
CPU wants the control of the bus, the DMA
transfer is immediately stopped. Thus the cycle n‹S>Vr h¡, `h DMA H$mo amoH$ XoVm h¡ & AWm©V² DMA
for which CPU is not using system bus is stolen H§$Q´>moba Cg g_` H$mo MwamVm h¡ {Og g_` CPU H$mo ~g
by DMA controller. It is a slower data transfer H$s Amdí`H$Vm Zht hmoVr& `h EH$ Yr_r J{V go H$m`© H$aZo
but it gives more efficient utilisation of CPU. dmbr {d{Y h¡Ÿ& bo{H$Z BgH$m _w»` \$m`Xm `h h¡ {H$ CPU
H$m à^mdr Cn`moJ hmoVm h¡Ÿ& 
Review Questions

Q.1. Explain Program Controlled Data Transfer.
àmoJ«m_ H$ÊQ´>moëS>> S>mQ>m Q´>m§g\$a H$m dU©Z H$s{OEŸ&
Q.2. What is DMA? What is the role of DMA controller? Explain Burst mode and cycle stealing
mode of data transfer.
DMA Š`m h¡? DMA H$ÊQ´>moba H$s ^y{_H$m Š`m h¡? S>mQ>m Q´>m§g\$a Ho$ ~ñQ>© _moS> VWm gm`H$b ñQ>rqbJ _moS>
H$mo g_PmB`oŸ&