Page 408 - FUNDAMENTALS OF COMPUTER

NPP

408 Fundamentals of Computers NPP

CLD: Clear Direction flag, DF = 0 is obtained. CLD: Šcr`a S>mBaoŠeZ âcoJ, DF = 0 àmßV
hmoVm h¡&
NOP: No operation; do not perform any op- NOP: H$moB© Am°naoeZ Zht H$aVm h¡, Q>mB_ {S>co Ho$ {cE
eration, used to insert time delay. Cn`moJ {H$`m OmVm h¡&
HLT: Halt; Stop any further processing. A HLT: AmJo H$s àmogoqgJ amoH$Vm h¡& EH$ [agoQ> FFFFOH
reset will cause to move at FFFFOH.
na OmZo H$m H$maU hmoJm&
WAIT: Wait unitl TEST pin goes at low. When- WAIT: d¡Q> H$aVm h¡ O~ VH$ {H$ TEST {nZ ZrMo Zht
ever 8086 finds WAIT instruction it Mcr OmVr h¡& O~ H$^r 8086 d¡Q> BÝñQ´>ŠeZ
enters into wait state. It continuously
examine TEST pin. As soon as test pin nmVm h¡ Vmo `h d¡Q> ñQ>oQ> _| Mcm OmVm h¡& `h
is made low it goes to the instruction {ZaÝVa TEST {nZ H$m narjU H$aVm h¡& O¡go
following the WAIT instruction. hr Q>oñQ> {nZ cmo hmoVr h¡ Vmo `h d¡Q> BÝñQ´>ŠeZ
Ho$ AmJo H$s BÝñQ´>ŠeZ na Mcr OmVr h¡&
ESC: Escape; 8086 considers this instruction ESC: 8086 Bgo EH$ NOP BÝñQ´>ŠeZ _mZVm h¡&
to be a NOP. Coprocessor instructions H$moàmogoga BÝñQ´>ŠeÝg ESC BÝñQ´>ŠeZ go Ow‹S>o
are associated with ESC instruction.
Therefore 8086 ignores it. hmoVo h¢& Bg{cE 8086 BgH$s AdhocZm H$aVm
h¡&
LOCK: Lock the bus for coprocessors. The bus LOCK: ~g H$mo H$moàmogoga Ho$ {cE cm°H$ H$a XoVm h¡& ~g
is locked for next instruction execu- H$mo _ëQ>ràmogoga {gñQ>_ (_¡pŠO__ _moS>) _|
tion used in multiprocessor system Cn`moJ Ho$ {cE AJco BÝQ´>ŠeZ EŠOrŠ`yeZ H$mo
(maximum mode)
cm°H$ H$aVm h¡&
5.4.5 Types of CPU Organisation 5.4.5 CPU Am°J}ZmBOoeZ Ho$ àH$ma

Internal organisation of CPU registers may CPU a{OñQ>g© H$m BÝQ>Z©c Am°J}ZmBOoeZ VrZ {^ÝZ
take three different forms:
ê$n co gH$Vm h¡:
1. Single Accumulator Organisation 1. qgJc EŠ`y_wcoQ>a Am°J}ZmBOoeZ
2. General Register Organisation 2. OZac a{OñQ>a Am°J}ZmBOoeZ
3. Stack Organisation 3. ñQ>¡H$ Am°J}ZmBOoeZ
1. Single Accumulator Organisation 1. qgJc EŠ`y_wcoQ>a Am°J}ZmBOoeZ
All arithmetic and logical operations are g^r A[aW_o{Q>H$ VWm cm°{OH$c Am°naoeÝg EH$
performed with an implied register called Ac- BåßcmBS> a{OñQ>a Ho$ gmW gånÝZ {H$`o OmVo h¢ {Ogo
cumulator. Therefore only one operand is speci- EŠ`y_wcoQ>a H$hm OmVm h¡& Bg{cE Ho$dc EH$ Am°naoÝS> hr
fied in computational instructions. Consider H$åß`yQ>oeZc BÝñQ´>ŠeÝg _| {ZYm©[aV {H$`m OmVm h¡&
following:
{ZåZ{c{IV na {dMma H$a|:
ADD Y
If Y is defined as a memory word following `{X Y EH$ _o_moar dS>© Ho$ ê$n _| n[a^m{fV {H$`m J`m
microoperations would be performed: h¡ Vmo {ZåZ{c{IV _mBH«$moAm°naoeÝg gånÝZ hm|Jo: