Page 6 - vinafix.com_Compal AAL15 LA-D071P r1.0

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+3VS
UC1A SKL-U
2 1 PCH_HDMI_CLK E55 C47
RC175 2.2K_0402_5% <33,34> HDMI_CRT_N0 F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TX0_DN <32>
<33,34>
EDP_TX0_DP <32>
HDMI_CRT_P0
2 1 PCH_HDMI_DATA E58 DDI1_TXP[0] EDP_TXP[0] D46
RC178 2.2K_0402_5% <33,34> HDMI_CRT_N1 F58 DDI1_TXN[1] EDP_TXN[1] C45 EDP_TX1_DN <32>
2 1 WLAN_RADIO_DIS# <33,34> HDMI_CRT_P1 F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TX1_DP <32>
D RE439 10K_0402_5% <33> HDMI_DATA0# G53 DDI1_TXN[2] EDP_TXN[2] B45 D
<33> HDMI_DATA0 F56 DDI1_TXP[2] EDP_TXP[2] A47 +3VALW_PCH
<33> HDMI_CLK# G56 DDI1_TXN[3] EDP_TXN[3] B47
<33> HDMI_CLK DDI1_TXP[3] EDP_TXP[3] SIO_EXT_SMI# 2 1
C50 E45 EDP_AUX_DN <32> Change "SIO_EXT_SMI#" 10K_0402_5% RC239
D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 PU to "+3VALW_PCH" For SW
C52 DDI2_TXP[0] EDP_AUXP EDP_AUX_DP <32> Reserve "+3VS" PU +3VS
D52 DDI2_TXN[1] B52 2015/5/19 Jason
A50 DDI2_TXP[1] EDP_DISP_UTIL SIO_EXT_SMI# 2 @ 1
B50 DDI2_TXN[2] G50 PCH_DPB_AUXN 10K_0402_5% RC236
D51 DDI2_TXP[2] DDI1_AUXN F50 PCH_DPB_AUXP PCH_DPB_AUXN <34> CPU_DP2_AUXN 2 @ 1
C51 DDI2_TXN[3] DDI1_AUXP E48 CPU_DP2_AUXN PCH_DPB_AUXP <34> 100K_0402_5% RC179
DDI2_TXP[3] DDI2_AUXN F48 CPU_DP2_AUXP PCH_DPB_AUXN 2 1
DDI2_AUXP G46 CPU_DP3_AUXN Jason 6/24 100K_0402_5% RC181
DISPLAY SIDEBANDS DDI3_AUXN F46 CPU_DP3_AUXP PAD~D @ @ T1 T2 Short Pad
PCH_HDMI_CLK L13 DDI3_AUXP PAD~D
<33> PCH_HDMI_CLK PCH_HDMI_DATA L12 GPP_E18/DDPB_CTRLCLK L9 CPU_HDMI_HPD 1 @ 2 HDMI_CRT_DET PCH_DPB_AUXP 2 1
<33> PCH_HDMI_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 RC385 0_0402_5% HDMI_CRT_DET <33,34> 100K_0402_5% RC182
N7 GPP_E14/DDPC_HPD1 L6 CPU_DP2_AUXP 2 1
N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9 CPU_CRT_HPD 1 SIO_EXT_SMI# <29> 100K_0402_5% @ RC180
@
2
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 RC386 0_0402_5% EDP_HPD 2 1
N11 GPP_E17/EDP_HPD EDP_HPD <32> 100K_0402_5% @ RC1
N12 GPP_E22/DDPD_CTRLCLK R12 L_BKLT_EN_EC HDMI_CRT_DET 2 1
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN R11 L_BKLT_EN_EC <29> 100K_0402_5% @ RC312
RC2 1 2 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 L_BKLT_CTRL <32> L_BKLT_EN_EC 2 1
+1.0VS_VCCIO EDP_RCOMP 1 OF 20 EDP_VDDEN EDP_VDD_EN <32> 100K_0402_5% RC390
COMPENSATION PU FOR eDP SKL-U_BGA1356
CAD Note:Trace width=20 mils ,Spacing=25mil, SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0
Max length=100 mils.
C C
UC1I SKL_ULT
CSI-2
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B B38 CSI2_DN3 CSI2_CLKN3 A26 B
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC3 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7 WLAN_RADIO_DIS# WLAN_RADIO_DIS# <36>
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 EMMC_RCOMP 1 2
EMMC_RCOMP RC4 200_0402_1%
SKL-U_BGA1356 9 OF 20
A A
DELL CONFIDENTIAL/PROPRIETARY
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Compal Electronics, Inc.mpal Electronics, Inc.mpal Electronics, Inc.
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Titletletle
CPU (1/14)U (1/14)U (1/14)
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CP
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Sizezeze Do Re Re Revvv
Document Numbercument Numbercument Number
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0(A00)0(A00)0(A00)
1. 1.
LA
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-D071P-D071P-D071P
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Da Th Th Thursday, July 09, 2015ursday, July 09, 2015ursday, July 09, 2015 Sh 6 6 6 of of of 64
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