Page 8 - vinafix.com_Compal AAL15 LA-D071P r1.0

5 4 3 2 1
+3VS
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1 2 QC2A
DMN66D0LDW-7_SOT363-6
PCH EDS R0.7 p.235~236
UC1E SKL-U SMBCLK 6 1 PCH_SMBCLK <20,21,34>
SPI - FLASH SMBUS, SMLINK 5 QC2B
PCH_SPI_CLK_R1 AV2 DMN66D0LDW-7_SOT363-6
PCH_SPI_D1_R1 AW3 SPI0_CLK R7 SMBCLK SMBDATA 3 4 PCH_SMBDAT <20,21,34>
PCH_SPI_D0_R1 AV3 SPI0_MISO GPP_C0/SMBCLK R8 SMBDATA
PCH_SPI_D2_R1 AW2 SPI0_MOSI GPP_C1/SMBDATA R10 PCH_SMB_ALERT# +3VALW_PCH
PCH_SPI_D3_R1 AU4 SPI0_IO2 GPP_C2/SMBALERT#
PCH_SPI_CS#0_R1 AU3 SPI0_IO3 R9 SML0_SMBCLK
D AU2 SPI0_CS0# GPP_C3/SML0CLK W2 SML0_SMBDATA D
AU1 SPI0_CS1# GPP_C4/SML0DATA W1 GPP_C5 2 QC5A DSX@
+3VS SPI0_CS2# GPP_C5/SML0ALERT# DMN66D0LDW-7_SOT363-6
W3 SML1CLK SML1CLK 1 6
SPI - TOUCH GPP_C6/SML1CLK V3 SML1DATA GPU_THM_SMBCLK <29,38,57>
1 ONE_DIMM# M2 GPP_C7/SML1DATA AM7 GPP_B23 5 QC5B DSX@
M3 GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT# DMN66D0LDW-7_SOT363-6
J4 GPP_D2/SPI1_MISO SML1DATA 4 3
@
V1 GPP_D3/SPI1_MOSI GPU_THM_SMBDAT <29,38,57>
V2 GPP_D21/SPI1_IO2
2 GPP_D22/SPI1_IO3
RC267
+3VS M1 LPC N_DSX@
10K_0402_5%
ONE_DIMM# GPP_D0/SPI1_CS# AY13 SML1CLK 1 2 GPU_THM_SMBCLK
GPP_A1/LAD0/ESPI_IO0 BA13 LPC_LAD0 <29> RC0801 N_DSX@ 0_0402_5%
1 1 C LINK GPP_A2/LAD1/ESPI_IO1 BB13 LPC_LAD1 <29> SML1DATA 1 2 GPU_THM_SMBDAT
LPC_LAD2 <29>
GPP_A3/LAD2/ESPI_IO2
RC13 10K_0402_5% G3 CL_CLK GPP_A5/LFRAME#/ESPI_CS# AY12 SUS_STAT#/LPCPD# LPC_LFRAME# <29> RC0802 0_0402_5%
LPC_LAD3 <29>
GPP_A4/LAD3/ESPI_IO3
BA12
G2
CL_DATA
G1
BA11
RC268
2 2 CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# EMI@ RC16 1 2 22_0402_5% CLK_DP2VGA <34> +3VS
10K_0402_5%
<29> SIO_RCIN# AW13 GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK AW9 PCI_CLK_LPC0 EMI@ RC18 1 2 2 22_0402_5% CLK_PCI_LPC_MEC <29>
PCI_CLK_LPC1
22_0402_5%
AY9
EMI@
RC22 1
AY11 GPP_A10/CLKOUT_LPC1 AW11 CLKRUN# CLK_PCI_LPDEBUG <29> PCH_SMBDAT 2 1
<29> SERIRQ GPP_A6/SERIRQ GPP_A8/CLKRUN# CLKRUN# <29> 2.2K_0402_5% RN19
DIMM Detect +3VS RC21 1 2 10K_0402_1% PCH_SMBCLK 2 1
SKL-U_BGA1356 5 OF 20 2.2K_0402_5% RN20
HIGH 1 DIMM +3VALW_PCH
LOW 2 DIMM
SMBCLK 1 2
RC355 1 CMC@ 2 1K_0402_1% PCH_SPI_D0_R1 RC12 1K_0402_5%
<14> XDP_SPI_SI SMBDATA 1 2
RC354 1 CMC@ 2 1K_0402_1% PCH_SPI_D2_R1 Reserve for RF RC14 1K_0402_5%
<14> XDP_SPI_IO2
C SML1CLK 1 2 C
RC21/44 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for XDP CLK_PCI_LPC_MEC 2 1 RC15 1K_0402_5%
12P_0402_50V8J @EMI@ SML1DATA 1 2
CC4 RC17 1K_0402_5%
PCH_SPI_CLK_0_R SML0_SMBCLK 1 2
CLK_PCI_LPDEBUG 2 1 RC19 1K_0402_5%
12P_0402_50V8J @EMI@ SML0_SMBDATA 1 2
2 CC5 RC20 1K_0402_5%
+3.3V_SPI SUS_STAT#/LPCPD# 1 2
@ RC369 8.2K_0402_5%
PCH_SPI_D1_R1 RC317 1 2 33_0402_5% PCH_SPI_D1_0_R
RC29
PCH_SPI_D0_R1 RC318 1 2 33_0402_5% PCH_SPI_D0_0_R PCH_SPI_D1_0_R <29> +3VS
@EMI@
33_0402_5% 1
1 2 PCH_SPI_CS#0_R1 PCH_SPI_CLK_R1 RC319 1 2 33_0402_5% PCH_SPI_CLK_0_R PCH_SPI_D0_0_R <29>
RC339 4.7K_0402_5% PCH_SPI_D3_R1 RC320 1 2 33_0402_5% PCH_SPI_D3_0_R PCH_SPI_CLK_0_R <29>
1 2 PCH_SPI_D2_R1 PCH_SPI_D2_R1 RC327 1 2 33_0402_5% PCH_SPI_D2_0_R
2 RC30 1K_0402_5% CLKRUN# 1 2
1 @ 2 PCH_SPI_D3_R1 RC27 8.2K_0402_5%
CC8
RC31 1K_0402_5%
1
@EMI@
1 2 PCH_SPI_D3_R1
33P_0402_50V8J
RC316 1K_0402_5% +3VALW_PCH
PCH_SMB_ALERT# 1 @ 2
RC23 8.2K_0402_5%
TLS CONFIDENTIALITY
9/5 MOW
Option 1: Implement a 1 kOhm pull-down resistor on the signal and de-populate the HIGH ENABLE
required 1 kOhm pull-up resistor. In this case, customers must ensure that the SPI LOW(DEFAULT) DISABLE
B flash device on the platform has HOLD functionality disabled by default. B
Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms +3VALW_PCH
with ES and SKL S/H platforms with pre-ES1/ES1 samples.
GPP_C5 1 @ 2
+3.3V_SPI RC25 10K_0402_5%
CC9
1 2 EC interface
128Mb Flash ROM
Short Pad 0.1U_0402_25V6 HIGH ESPI
UC5
PCH_SPI_CS#0_R1 RC37 1 @ 2 0_0402_5% PCH_SPI_CS#0_R2 1 8 LOW(DEFAULT) LPC
<29> PCH_SPI_CS#0_R1 PCH_SPI_D1_0_R RC329 1 2 15_0402_1% PCH_SPI_D1_0_R3 2 /CS VCC 7 PCH_SPI_D3_0_R3 RC331 1 2 15_0402_1% PCH_SPI_D3_0_R
PCH_SPI_D2_0_R RC330 1 2 15_0402_1% PCH_SPI_D2_0_R3 3 IO1 IO3 6 PCH_SPI_CLK_0_R3 RC332 1 2 15_0402_1% PCH_SPI_CLK_0_R
4 IO2 CLK 5 PCH_SPI_D0_0_R3 RC333 1 2 15_0402_1% PCH_SPI_D0_0_R
GND IO0 +3VALW_PCH
W25Q128FVSIQ_SO8 Modify Value to 150k for WW52 MOW
2015/03/03 Jason
Main: GPP_B23 1 CMC@ 2
SA00005VV10, S IC FL 128M W25Q128FVSIQ SOIC8P SPI ROM RC365 150K_0402_5%
2nd:
SA00008KK00, S IC FL 128M GD25B128CSIGR SOP 8P 3.3V
SA00006PD00, S IC FL 128M EN25QH128A-104HIP SOP 8P EXI BOOT STALL BYPASS
Jason 2015/03/04 HIGH ENABLE
LOW(DEFAULT) DISABLE
A A
DELL CONFIDENTIAL/PROPRIETARY
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Compal Electronics, Inc.mpal Electronics, Inc.mpal Electronics, Inc.
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
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