Page 62 - vinafix.com_Compal AAL15 LA-D071P r1.0

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M_DA[63..0]
<60,61> M_DA[63..0] Reduce Vref Circuit
M_MA[15..0] for Spacing saving.
<60,61> M_MA[15..0] UV19 @ UV17 @ UV16 @ UV18 @
M_DQM[7..0] VREFCA_UV7 M8 E3 M_DA16 VREFCA_UV8 M8 E3 M_DA12 VREFCA_UV9 M8 E3 M_DA54 VREFCA_UV10 M8 E3 M_DA45
<60,61> M_DQM[7..0] VREFDQ_UV7 H1 VREFCA DQL0 F7 M_DA19 VREFCA_UV7 H1 VREFCA DQL0 F7 M_DA10 VREFDQ_UV9 H1 VREFCA DQL0 F7 M_DA52 VREFDQ_UV10 H1 VREFCA DQL0 F7 M_DA42
M_DQS[7..0] VREFDQ DQL1 F2 M_DA17 VREFDQ DQL1 F2 M_DA13 VREFDQ DQL1 F2 M_DA51 VREFDQ DQL1 F2 M_DA46
<60,61> M_DQS[7..0] M_MA0 N3 DQL2 F8 M_DA23 M_MA0 N3 DQL2 F8 M_DA8 M_MA0 N3 DQL2 F8 M_DA48 M_MA0 N3 DQL2 F8 M_DA41
M_DQS#[7..0] M_MA1 P7 A0 DQL3 H3 M_DA22 M_MA1 P7 A0 DQL3 H3 M_DA14 M_MA1 P7 A0 DQL3 H3 M_DA55 M_MA1 P7 A0 DQL3 H3 M_DA44
<60,61> M_DQS#[7..0] M_MA2 P3 A1 DQL4 H8 M_DA20 M_MA2 P3 A1 DQL4 H8 M_DA11 M_MA2 P3 A1 DQL4 H8 M_DA49 M_MA2 P3 A1 DQL4 H8 M_DA43
M_MA3 N2 A2 A3 DQL5 G2 M_DA21 M_MA3 N2 A2 A3 DQL5 G2 M_DA15 M_MA3 N2 A2 A3 DQL5 G2 M_DA53 M_MA3 N2 A2 A3 DQL5 G2 M_DA47
DQL6
DQL6
DQL6
DQL6
M_MA4 P8 H7 M_DA18 M_MA4 P8 H7 M_DA9 M_MA4 P8 H7 M_DA50 M_MA4 P8 H7 M_DA40
M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7
VREFCA_UV7 M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5
<61> VREFCA_UV7 A6 A6 A6 A6
A M_MA7 R2 D7 M_DA3 M_MA7 R2 D7 M_DA27 M_MA7 R2 D7 M_DA56 M_MA7 R2 D7 M_DA35 A
M_MA8 T8 A7 DQU0 C3 M_DA5 M_MA8 T8 A7 DQU0 C3 M_DA28 M_MA8 T8 A7 DQU0 C3 M_DA62 M_MA8 T8 A7 DQU0 C3 M_DA38
Reduce Vref Circuit for Spacing saving. M_MA9 R3 A8 DQU1 C8 M_DA0 M_MA9 R3 A8 DQU1 C8 M_DA24 M_MA9 R3 A8 DQU1 C8 M_DA59 M_MA9 R3 A8 DQU1 C8 M_DA34
M_MA10 L7 A9 DQU2 C2 M_DA7 M_MA10 L7 A9 DQU2 C2 M_DA31 M_MA10 L7 A9 DQU2 C2 M_DA63 M_MA10 L7 A9 DQU2 C2 M_DA37
M_MA11 R7 A10/AP DQU3 A7 M_DA2 M_MA11 R7 A10/AP DQU3 A7 M_DA26 M_MA11 R7 A10/AP DQU3 A7 M_DA57 M_MA11 R7 A10/AP DQU3 A7 M_DA33
M_MA12 N7 A11 DQU4 A2 M_DA6 M_MA12 N7 A11 DQU4 A2 M_DA30 M_MA12 N7 A11 DQU4 A2 M_DA60 M_MA12 N7 A11 DQU4 A2 M_DA39
M_MA13 T3 A12 DQU5 B8 M_DA1 M_MA13 T3 A12 DQU5 B8 M_DA25 M_MA13 T3 A12 DQU5 B8 M_DA58 M_MA13 T3 A12 DQU5 B8 M_DA32
DQU6
A13
A13
DQU6
A13
A13
DQU6
DQU6
M_MA14 T7 A3 M_DA4 M_MA14 T7 A3 M_DA29 M_MA14 T7 A3 M_DA61 M_MA14 T7 A3 M_DA36
M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7
A15/BA3 +1.35V_MEM_GFX A15/BA3 +1.35V_MEM_GFX A15/BA3 +1.35V_MEM_GFX A15/BA3 +1.35V_MEM_GFX
M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2
<60,61> M_BA0 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9
<60,61> M_BA1 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7
<60,61> M_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9 M_CLK1 J7 VDD N9 M_CLK1 J7 VDD N9
<60,61> M_CLK0 M_CLK#0 K7 CK VDD R1 M_CLK#0 K7 CK VDD R1 <60,61> M_CLK1 M_CLK#1 K7 CK VDD R1 M_CLK#1 K7 CK VDD R1
<60,61> M_CLK#0 M_CKE0 K9 CK VDD R9 M_CKE0 K9 CK VDD R9 <60,61> M_CLK#1 M_CKE1 K9 CK VDD R9 M_CKE1 K9 CK VDD R9
<60,61> M_CKE0 CKE/CKE0 VDD +1.35V_MEM_GFX CKE/CKE0 VDD +1.35V_MEM_GFX <60,61> M_CKE1 CKE/CKE0 VDD +1.35V_MEM_GFX CKE/CKE0 VDD +1.35V_MEM_GFX
VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1 VRAM_ODT1 K1 A1 VRAM_ODT1 K1 A1
<60,61> VRAM_ODT0 M_CS0B#1 L2 ODT/ODT0 VDDQ A8 M_CS0B#1 L2 ODT/ODT0 VDDQ A8 <60,61> VRAM_ODT1 M_CS1B#1 L2 ODT/ODT0 VDDQ A8 M_CS1B#1 L2 ODT/ODT0 VDDQ A8
<60> M_CS0B#1 CS/CS0 VDDQ CS/CS0 VDDQ <60> M_CS1B#1 CS/CS0 VDDQ CS/CS0 VDDQ
<60,61> M_RAS#0 M_RAS#0 K3 J3 RAS VDDQ C1 C9 M_RAS#0 J3 K3 RAS VDDQ C1 C9 <60,61> M_RAS#1 M_RAS#1 K3 J3 RAS VDDQ C1 M_RAS#1 K3 J3 RAS VDDQ C1
C9
C9
M_CAS#0
M_CAS#1
M_CAS#1
M_CAS#0
<60,61> M_CAS#0 M_WE#0 L3 CAS VDDQ D2 M_WE#0 L3 CAS VDDQ D2 <60,61> M_CAS#1 M_WE#1 L3 CAS VDDQ D2 M_WE#1 L3 CAS VDDQ D2
<60,61> M_WE#0 WE VDDQ E9 WE VDDQ E9 <60,61> M_WE#1 WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
M_DQS2 F3 VDDQ H2 M_DQS1 F3 VDDQ H2 M_DQS6 F3 VDDQ H2 M_DQS5 F3 VDDQ H2
M_DQS0 C7 DQSL VDDQ H9 M_DQS3 C7 DQSL VDDQ H9 M_DQS7 C7 DQSL VDDQ H9 M_DQS4 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
M_DQM2 E7 A9 M_DQM1 E7 A9 M_DQM6 E7 A9 M_DQM5 E7 A9
M_DQM0 D3 DML VSS B3 M_DQM3 D3 DML VSS B3 M_DQM7 D3 DML VSS B3 M_DQM4 D3 DML VSS B3
B DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1 B
VSS G8 VSS G8 VSS G8 VSS G8
M_DQS#2 G3 VSS J2 M_DQS#1 G3 VSS J2 M_DQS#6 G3 VSS J2 M_DQS#5 G3 VSS J2
M_DQS#0 B7 DQSL VSS J8 M_DQS#3 B7 DQSL VSS J8 M_DQS#7 B7 DQSL VSS J8 M_DQS#4 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9
<60,61> DRAM_RST RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1 J1 B1 1 J1 B1 1 J1 B1 1 J1 B1
L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9
RV118 J9 NC/CS1 VSSQ D1 RV110 J9 NC/CS1 VSSQ D1 RV117 J9 NC/CS1 VSSQ D1 RV114 J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
V_4G@ NCZQ1 VSSQ E2 V_4G@ 2 NCZQ1 VSSQ E2 V_4G@ 2 NCZQ1 VSSQ E2 V_4G@ 2 NCZQ1 VSSQ E2
2 VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
M_CLK0 RV95 1 2 VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
80.6_0402_1% VSSQ VSSQ M_CLK1 RV116 1 2 VSSQ VSSQ
V_4G@ 96-BALL 96-BALL 80.6_0402_1% 96-BALL 96-BALL
M_CLK#0RV111 1 2 SDRAM DDR3 SDRAM DDR3 V_4G@ SDRAM DDR3 SDRAM DDR3
80.6_0402_1% H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96 M_CLK#1RV112 1 2 H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96
V_4G@ 1 80.6_0402_1%
CV271 V_4G@ 1
.01U_0402_16V7-K CV279
V_4G@ .01U_0402_16V7-K
2 V_4G@
2
C C
+1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX
1 1 1 1
RV96 This circuit is share with 3pcs VRAM. RV113 RV234 RV258
4.99K_0402_1% Please keep stuff when DIS@. 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DIS@ V_4G@ V_4G@ V_4G@
+1.35V_MEM_GFX +1.35V_MEM_GFX
2 2 2 2
VREFCA_UV7 VREFCA_UV8 VREFCA_UV9 VREFCA_UV10
1 1 1 1
1 1 1 1
RV115 CV298 RV97 CV300 RV251 CV264 RV248 CV275 CV288 1 CV281 1 CV285 1 CV274 1 CV229 1 CV224 1 CV278 1 CV294 1 CV269 1 CV302 1 CV266 1 CV287 1 CV228 1 CV268 1 CV272 1 CV296 1 CV282 1 CV301 1 CV276 1 CV292 1
4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K
DIS@ DIS@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K
2 2 2 2 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@
V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@
+1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX
1 1 1
RV252 RV256 RV247 CV295 1 CV299 1 CV227 1 CV277 1 CV270 1 CV283 1 CV291 1 CV289 1 CV290 1 CV297 1 CV284 1 CV303 1 CV225 1 CV280 1 CV226 1 CV286 1
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
V_4G@ V_4G@ V_4G@ 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
D 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 D
VREFDQ_UV7 Reduce Vref Circuit for Spacing saving. VREFDQ_UV9 VREFDQ_UV10
VREFDQ_UV8 Share with VREFCA_UV7
1 1 1
1 1 1
RV249 CV265 RV253 CV293 RV259 CV273 V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@
4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@
V_4G@ V_4G@ V_4G@ V_4G@ V_4G@ V_4G@
2 2 2
2 2 2
Compal Electronics, Inc.mpal Electronics, Inc.mpal Electronics, Inc.
Co
Se Security Classificationcurity Classificationcurity Classification C C Compal Secret Dataompal Secret Dataompal Secret Data Co
Se
2016/
2016/07/3107/3107/31
2015/
2015/
I I Issued Datessued Datessued Date 2015/07/0907/0907/09 De 2016/ Ti Ti Titletletle
Deciphered Dateciphered Dateciphered Date
De
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL VRAM A UpperVRAM A UpperVRAM A Upper
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Do
Si Si
Re
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Do
Re
Sizezeze
AN
AN AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DD TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DD TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Numbercument Numbercument Number Revvv
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA 1. 1. 1.0(A00)0(A00)0(A00)
DE
LA
LA-D071P-D071P-D071P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomCustomCustom
MA
MA
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:te:te: Thursday, July 09, 2015ursday, July 09, 2015ursday, July 09, 2015 Sh Sh Sheeteeteet 62 62 62 of of of 64 64 64
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