Page 61 - vinafix.com_Compal AAL15 LA-D071P r1.0

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M_DA[63..0] Reduce Vref Circuit
<60,62> M_DA[63..0] for Spacing saving. UV15 @ UV12 @ UV13 @ UV14 @
M_MA[15..0]
<60,62> M_MA[15..0] VREFCA_UV3 M8 E3 M_DA19 VREFCA_UV4 M8 E3 M_DA10 VREFCA_UV5 M8 E3 M_DA52 VREFCA_UV6 M8 E3 M_DA42
M_DQM[7..0] VREFCA_UV7 H1 VREFCA DQL0 F7 M_DA16 VREFDQ_UV4 H1 VREFCA DQL0 F7 M_DA12 VREFDQ_UV5 H1 VREFCA DQL0 F7 M_DA54 VREFDQ_UV6 H1 VREFCA DQL0 F7 M_DA47
<60,62> M_DQM[7..0] VREFDQ DQL1 F2 M_DA23 VREFDQ DQL1 F2 M_DA8 VREFDQ DQL1 F2 M_DA48 VREFDQ DQL1 F2 M_DA41
M_DQS[7..0] M_MA0 N3 DQL2 F8 M_DA17 M_MA0 N3 DQL2 F8 M_DA13 M_MA0 N3 DQL2 F8 M_DA51 M_MA0 N3 DQL2 F8 M_DA45
<60,62> M_DQS[7..0] M_MA1 P7 A0 DQL3 H3 M_DA18 M_MA1 P7 A0 DQL3 H3 M_DA11 M_MA1 P7 A0 DQL3 H3 M_DA50 M_MA1 P7 A0 DQL3 H3 M_DA40
M_DQS#[7..0] M_MA2 P3 A1 DQL4 H8 M_DA21 M_MA2 P3 A1 DQL4 H8 M_DA14 M_MA2 P3 A1 DQL4 H8 M_DA53 M_MA2 P3 A1 DQL4 H8 M_DA46
<60,62> M_DQS#[7..0] M_MA3 N2 A2 DQL5 G2 M_DA20 M_MA3 N2 A2 DQL5 G2 M_DA9 M_MA3 N2 A2 DQL5 G2 M_DA49 M_MA3 N2 A2 DQL5 G2 M_DA43
M_MA4 P8 A3 A4 DQL6 H7 M_DA22 M_MA4 P8 A3 A4 DQL6 H7 M_DA15 M_MA4 P8 A3 A4 DQL6 H7 M_DA55 M_MA4 P8 A3 A4 DQL6 H7 M_DA44
DQL7
DQL7
DQL7
DQL7
M_MA5 P2 M_MA5 P2 M_MA5 P2 M_MA5 P2
VREFCA_UV7 M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5 M_MA6 R8 A5
<62> VREFCA_UV7 A6 A6 A6 A6
M_MA7 R2 D7 M_DA5 M_MA7 R2 D7 M_DA28 M_MA7 R2 D7 M_DA62 M_MA7 R2 D7 M_DA38
A M_MA8 T8 A7 DQU0 C3 M_DA3 M_MA8 T8 A7 DQU0 C3 M_DA27 M_MA8 T8 A7 DQU0 C3 M_DA56 M_MA8 T8 A7 DQU0 C3 M_DA35 A
Reduce Vref Circuit for Spacing saving. M_MA9 R3 A8 A9 DQU1 C8 M_DA7 M_MA9 R3 A8 A9 DQU1 C8 M_DA31 M_MA9 R3 A8 A9 DQU1 C8 M_DA63 M_MA9 R3 A8 A9 DQU1 C8 M_DA37
DQU2
DQU2
DQU2
DQU2
M_MA10 L7 C2 M_DA0 M_MA10 L7 C2 M_DA24 M_MA10 L7 C2 M_DA59 M_MA10 L7 C2 M_DA34
M_MA11 R7 A10/AP DQU3 A7 M_DA4 M_MA11 R7 A10/AP DQU3 A7 M_DA29 M_MA11 R7 A10/AP DQU3 A7 M_DA61 M_MA11 R7 A10/AP DQU3 A7 M_DA36
M_MA12 N7 A11 DQU4 A2 M_DA1 M_MA12 N7 A11 DQU4 A2 M_DA25 M_MA12 N7 A11 DQU4 A2 M_DA58 M_MA12 N7 A11 DQU4 A2 M_DA32
M_MA13 T3 A12 DQU5 B8 M_DA6 M_MA13 T3 A12 DQU5 B8 M_DA30 M_MA13 T3 A12 DQU5 B8 M_DA60 M_MA13 T3 A12 DQU5 B8 M_DA39
M_MA14 T7 A13 DQU6 A3 M_DA2 M_MA14 T7 A13 DQU6 A3 M_DA26 M_MA14 T7 A13 DQU6 A3 M_DA57 M_MA14 T7 A13 DQU6 A3 M_DA33
A14
DQU7
DQU7
A14
DQU7
A14
A14
DQU7
M_MA15 M7 M_MA15 M7 M_MA15 M7 M_MA15 M7
A15/BA3 +1.35V_MEM_GFX A15/BA3 +1.35V_MEM_GFX A15/BA3 +1.35V_MEM_GFX A15/BA3 +1.35V_MEM_GFX
M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2 M_BA0 M2 B2
<60,62> M_BA0 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9 M_BA1 N8 BA0 VDD D9
<60,62> M_BA1 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7 M_BA2 M3 BA1 VDD G7
<60,62> M_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9 M_CLK1 J7 VDD N9 M_CLK1 J7 VDD N9
<60,62> M_CLK0 M_CLK#0 K7 CK VDD R1 M_CLK#0 K7 CK VDD R1 <60,62> M_CLK1 M_CLK#1 K7 CK VDD R1 M_CLK#1 K7 CK VDD R1
<60,62> M_CLK#0 M_CKE0 K9 CK VDD R9 M_CKE0 K9 CK VDD R9 <60,62> M_CLK#1 M_CKE1 K9 CK VDD R9 M_CKE1 K9 CK VDD R9
<60,62> M_CKE0 CKE/CKE0 VDD +1.35V_MEM_GFX CKE/CKE0 VDD +1.35V_MEM_GFX <60,62> M_CKE1 CKE/CKE0 VDD +1.35V_MEM_GFX CKE/CKE0 VDD +1.35V_MEM_GFX
VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1 VRAM_ODT1 K1 A1 VRAM_ODT1 K1 A1
<60,62> VRAM_ODT0 M_CS0B#0 L2 ODT/ODT0 VDDQ A8 M_CS0B#0 L2 ODT/ODT0 VDDQ A8 <60,62> VRAM_ODT1 M_CS1B#0 L2 ODT/ODT0 VDDQ A8 M_CS1B#0 L2 ODT/ODT0 VDDQ A8
<60> M_CS0B#0 M_RAS#0 J3 CS/CS0 VDDQ C1 M_RAS#0 J3 CS/CS0 VDDQ C1 <60> M_CS1B#0 M_RAS#1 J3 CS/CS0 VDDQ C1 M_RAS#1 J3 CS/CS0 VDDQ C1
<60,62> M_RAS#0 M_CAS#0 K3 RAS VDDQ C9 M_CAS#0 K3 RAS VDDQ C9 <60,62> M_RAS#1 M_CAS#1 K3 RAS VDDQ C9 M_CAS#1 K3 RAS VDDQ C9
<60,62> M_CAS#0 M_WE#0 L3 CAS VDDQ D2 M_WE#0 L3 CAS VDDQ D2 <60,62> M_CAS#1 M_WE#1 L3 CAS VDDQ D2 M_WE#1 L3 CAS VDDQ D2
<60,62> M_WE#0 WE VDDQ E9 WE VDDQ E9 <60,62> M_WE#1 WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
M_DQS2 F3 VDDQ H2 M_DQS1 F3 VDDQ H2 M_DQS6 F3 VDDQ H2 M_DQS5 F3 VDDQ H2
M_DQS0 C7 DQSL VDDQ H9 M_DQS3 C7 DQSL VDDQ H9 M_DQS7 C7 DQSL VDDQ H9 M_DQS4 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
M_DQM2 E7 A9 M_DQM1 E7 A9 M_DQM6 E7 A9 M_DQM5 E7 A9
M_DQM0 D3 DML VSS B3 M_DQM3 D3 DML VSS B3 M_DQM7 D3 DML VSS B3 M_DQM4 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
B VSS G8 VSS G8 VSS G8 VSS G8 B
M_DQS#2 G3 DQSL VSS J2 M_DQS#1 G3 DQSL VSS J2 M_DQS#6 G3 DQSL VSS J2 M_DQS#5 G3 DQSL VSS J2
VSS
VSS
VSS
VSS
M_DQS#0 B7 J8 M_DQS#3 B7 J8 M_DQS#7 B7 J8 M_DQS#4 B7 J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9
<60,62> DRAM_RST RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1 J1 B1 1 J1 B1 1 J1 B1 1 J1 B1
L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9
RV102 J9 NC/CS1 VSSQ D1 RV103 J9 NC/CS1 VSSQ D1 RV108 J9 NC/CS1 VSSQ D1 RV104 J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
VSSQ
VSSQ
NCZQ1
NCZQ1
NCZQ1
VSSQ
VSSQ
NCZQ1
DIS@ 2 VSSQ E2 DIS@ 2 VSSQ E2 DIS@ 2 VSSQ E2 DIS@ 2 VSSQ E2
VSSQ E8 F9 VSSQ E8 F9 VSSQ E8 F9 VSSQ E8 F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
M_CLK0 RV109 1 2 VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
VSSQ
VSSQ
VSSQ
VSSQ
1
80.6_0402_1% 96-BALL 96-BALL M_CLK1 RV98 80.6_0402_1% 2 96-BALL 96-BALL
M_CLK#0RV105 1 DIS@ 2 SDRAM DDR3 SDRAM DDR3 DIS@ SDRAM DDR3 SDRAM DDR3
80.6_0402_1% H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96 M_CLK#1RV99 1 2 H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96
DIS@ 1 80.6_0402_1%
CV206 DIS@ 1
.01U_0402_16V7-K CV247
DIS@ .01U_0402_16V7-K
2 DIS@
2
C C
+1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX
1 1 1 1
RV100 RV101 RV239 RV238 CV210 1 CV260 1 CV246 1 CV262 1 CV254 1 CV245 1 CV207 1 CV259 1 CV248 1 CV244 1 CV214 1 CV165 1 CV211 1 CV251 1 CV239 1 CV238 1 CV240 1 CV208 1 CV258 1 CV249 1
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DIS@ DIS@ DIS@ DIS@ .1U_0402_16V7K DIS@ .1U_0402_16V7K DIS@ .1U_0402_16V7K DIS@ DIS@ .1U_0402_16V7K DIS@ DIS@ .1U_0402_16V7K DIS@ .1U_0402_16V7K DIS@ DIS@ .1U_0402_16V7K DIS@ DIS@ DIS@ .1U_0402_16V7K DIS@ .1U_0402_16V7K DIS@ DIS@ .1U_0402_16V7K DIS@ 10U_0603_6.3V6M DIS@ 10U_0603_6.3V6M DIS@ 10U_0603_6.3V6M DIS@ 10U_0603_6.3V6M DIS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VREFCA_UV3 VREFCA_UV4 VREFCA_UV5 VREFCA_UV6
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
1 1 1 1
1 1 1 1
RV106 CV209 RV107 CV216 RV237 CV237 RV244 CV242
4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2 2 2 2 +1.35V_MEM_GFX
2 2 2 2
1 CV217 1 CV204 1 CV223 1 CV205 1 CV241 1 CV243 1 CV250 1 CV213 1 CV253 1 CV256 1 CV261 1 CV215 1 CV222 1 CV221 1 CV212 1
CV257
DIS@ DIS@ DIS@ 1U_0402_6.3V6K DIS@ 1U_0402_6.3V6K DIS@ DIS@ 1U_0402_6.3V6K DIS@ DIS@ DIS@ 1U_0402_6.3V6K DIS@ DIS@ 1U_0402_6.3V6K DIS@ 1U_0402_6.3V6K DIS@ DIS@ 1U_0402_6.3V6K DIS@ 1U_0402_6.3V6K DIS@
+1.35V_MEM_GFX +1.35V_MEM_GFX +1.35V_MEM_GFX 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
1 1 1
RV245 RV246 RV241
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
DIS@ DIS@ DIS@
D D
2 2 2
Reduce Vref Circuit for Spacing saving. VREFDQ_UV4 VREFDQ_UV5 VREFDQ_UV6
VREFDQ_UV3 Share with VREFCA_UV7 1 1 1
1 1 1
RV243 CV263 RV235 CV236 RV242 CV252
4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K 4.99K_0402_1% .1U_0402_16V7K
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2 2 2
Compal Electronics, Inc.mpal Electronics, Inc.mpal Electronics, Inc.
Co
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2 2 2 Security Classificationcurity Classificationcurity Classification C C Compal Secret Dataompal Secret Dataompal Secret Data Co
2016/
2015/07/0907/0907/09
2015/
2016/07/3107/3107/31
I I Issued Datessued Datessued Date 2015/ De 2016/ Titletletle
Ti Ti
Deciphered Dateciphered Dateciphered Date
De
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL VRAM A LowerVRAM A LowerVRAM A Lower
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Do
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Si Si
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AN
AN AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DD TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DD TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Do Document Numbercument Numbercument Number Re Revvv
1. 1.
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LA
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-D071P-D071P-D071P 1.0(A00)0(A00)0(A00)
DE
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CustomCustomCustom
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MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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Date:te:te: Th Thursday, July 09, 2015ursday, July 09, 2015ursday, July 09, 2015 Sheeteeteet 61 61 61 of of of 64 64 64
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