Page 63 - vinafix.com_Compal AAL15 LA-D071P r1.0

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Power-Up/Down Sequence 1. All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/μs.
2. It is recommended that the 3.3-V rail ramp up first.
3. It is recommended that the 0.95-V rail reach at least 90% of its nominal value
no later than 2 ms from the start of VDDC ramping up.
4. The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example
AMD PowerXpress? idle state), all the power rails are removed from the dGPU.
D The gate circuits must meet the slew rate requirement (such as ? 50 mV/μs). D
5. VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa).
6. For power down, reversing the ramp-up sequence is recommended.
AND PCH_PLTRST#_EC GPU
< 20mS < 20mS MCP GPP_B13 PCH_PLTRST# GATE AND
GATE PLT_RST_VGA# PERSTB
VDDR3(3.3V)
+3VGS >10uS
(DGPU_PWR_EN) GPP_D10 DGPU_HOLD_RST#
PCIE_VDDC(0.95V) GPP_D13 DGPU_PWR_EN
+0.95VSDGPU
(DGPU_PWR_EN with RC delay) DGPU_PWROK
1.8V_IO(1.8V) GPP_D18
+1.8VGS
(DGPU_PWR_EN with RC delay)
VDDC/VDDCI(0.8~1.15V)
+VGA_CORE
(DGPU_PWR_EN)
VMEMIO(1.35V or 1.5V)
C +1.35V_MEM_GFX > 100mS > 100mS (SW) +3VS 1 +3VGS C
(DGPU_PWROK with RC delay) DGPU_PWR_EN# LDO
PWRGOOD
DGPU_PWROK
+1.0V_PRIM +0.95VSDGPU +1.8V_PRIM +1.8VGS
PERSTb > 100uS DGPU_PWR_EN# LDO 2 DGPU_PWR_EN# LDO 2
PLT_RST_VGA#
Asserted Before PERSTb
REFCLK B+ +VGA_CORE +1.35V_MEM +1.35V_MEM_GFX
CLK_PEG_VGA/CLK_PEG_VGA# PWM 3 LDO 3
DGPU_PWR_EN# DGPU_PWROK
DEVICE Device in Device Hardware Reset Device CFG Accessible Device Powering down Device Powered down
or Working
Reset
No requirements
ZZZ ZZZ ZZZ
X7662631L81 X7662631L82 X7662631L83
2G_S@ 2G_H@ 2G_M@
ALT. GROUP PARTS SAMSUNG 2GB AAL25 ALT. GROUP PARTS HYNIX 2GB AAL25 ALT. GROUP PARTS MICRON 2GB AAL25
ZZZ ZZZ ZZZ
Hynix 1G Micron 1G X7662631L84 X7662631L85 X7662631L86
B B
4G_S@ 4G_H@ 4G_M@
RV15 1G_H@ RV16 1G_H@ RV15 1G_M@ RV16 1G_M@
ALT. GROUP PARTS SAMSUNG 4GB AAL25 ALT. GROUP PARTS HYNIX 4GB AAL25 ALT. GROUP PARTS MICRON 4GB AAL25
For AMD EXO-XT VRAM Only
8.45K_0402_1% 2K_0402_1% 4.53K_0402_1% 2K_0402_1%
Memory ID P/N Vendor Configuration Size
SD000000680 SD034200180 SD034453180 SD034200180
Samsung 2G Hynix 2G Micron 2G 000 SA000076P2L SAMSUNG 256MX16 K4W4G1646E-BC1A FBGA 96P 4GB
RV15 2G_S@ RV16 2G_S@ RV15 2G_H@ RV16 2G_H@ RV15 2G_M@ RV16 2G_M@ 110 SA00008DN0L HYNIX 256MX16 H5TC4G63CFR-N0C FBGA 96P 4GB
111 SA000077K0L Micron 256M16 MT41J256M16HA-093G:E FBGA 4GB
011 SA000076P2L SAMSUNG 256MX16 K4W4G1646E-BC1A FBGA 96P 2GB
6.98K_0402_1% 4.99K_0402_1% 4.53K_0402_1% 4.99K_0402_1% 3.24K_0402_1% 5.62K_0402_1%
SD000002680 SD034499180 SD034453180 SD034499180 SD034324180 SD034562180 100 SA00008DN0L HYNIX 256MX16 H5TC4G63CFR-N0C FBGA 96P 2GB
Samsung 4G Hynix 4G Micron 4G 101 SA000077K0L Micron 256M16 MT41J256M16HA-093G:E FBGA 2GB
RV16 4G_S@ RV15 4G_H@ RV16 4G_H@ RV15 4G_M@ For AMD MESO-LE VRAM Only
Memory ID P/N Vendor Configuration Size
011 SA000076P2L SAMSUNG 256MX16 K4W4G1646E-BC1A FBGA 96P 2GB
4.75K_0402_1% 3.4K_0402_1% 10K_0402_1% 4.75K_0402_1%
A A
SD034475180 SD034340180 SD034100280 SD034475180
100 SA00008DN0L HYNIX 256MX16 H5TC4G63CFR-N0C FBGA 96P 2GB
2015/5/19 Modify 101 SA000077K0L Micron 256M16 MT41J256M16HA-093G:E FBGA 2GB
Jason
C C
Security Classificationcurity Classificationcurity Classification
Se Compal Secret Datampal Secret Datampal Secret Data Compal Electronics, Inc.ompal Electronics, Inc.ompal Electronics, Inc.
Co
Co
Se
Ti Ti
2015/
2016/
2016/07/3107/3107/31
2015/
Dec
Deciphered Dateiphered Dateiphered Date
Is Is
Issued Datesued Datesued Date 2015/07/0907/0907/09 Dec 2016/ Titletletle
EXO
EXO/MESO_NOTE/MESO_NOTE/MESO_NOTE
EXO
TH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Si Si Sizezeze Do Do Document Numbercument Numbercument Number Re Re Revvv
TH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DD TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DD TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AN
AN
LA-D071P-D071P-D071P
LA
DE DE DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1. 1. 1.0(A00)0(A00)0(A00)
MA MA MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA
Sh
Da
Da Date:te:te: T T Thursday, July 09, 2015hursday, July 09, 2015hursday, July 09, 2015 Sh Sheeteeteet 63 63 63 of of of 64 64 64
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