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462                                                                Chapter 9



        could be achieved using the current version 7.51. EMPIRE XPU fully exploits the processor
        architecture by using the second and third level cache for multiple time stepping and
        parallelization on all built-in cores. High speed is achieved for all model sizes from 1 million
        FDTD up to more than 6500 Million FDTD cells.”


        REFERENCES

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        [4]    U. S. Inan,  R.  A. Marshall, Numerical Electromagnetics, The FDTD Method,
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        [9]    R. Rumpf, Introduction to CEM, Lecture 1, 2015
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               M.pdf
        [10]   Programming Models for Parallel Computing (Scientific and Engineering
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        [14]   G. D. Castillo, C. Mason, N. Chavannes, M. Okoniewski, High performance, high
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